first commit
This commit is contained in:
3850
Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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3850
Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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585
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h
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585
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h
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/**
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******************************************************************************
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* @file stm32f0xx_hal.h
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* @author MCD Application Team
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* @brief This file contains all the functions prototypes for the HAL
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* module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F0xx_HAL_H
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#define __STM32F0xx_HAL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_hal_conf.h"
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/** @addtogroup STM32F0xx_HAL_Driver
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* @{
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*/
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/** @addtogroup HAL
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* @{
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup HAL_Private_Macros
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* @{
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*/
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#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
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defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
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defined(STM32F070xB) || defined(STM32F030x6)
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#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
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#else
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#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
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(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
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#endif
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#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
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#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
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#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
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#if defined(STM32F091xC) || defined(STM32F098xx)
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#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
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((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
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((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
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#endif /* STM32F091xC || STM32F098xx */
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/**
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* @}
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*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup HAL_Exported_Constants HAL Exported Constants
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* @{
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*/
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/** @defgroup HAL_TICK_FREQ Tick Frequency
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* @{
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*/
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typedef enum
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{
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HAL_TICK_FREQ_10HZ = 100U,
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HAL_TICK_FREQ_100HZ = 10U,
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HAL_TICK_FREQ_1KHZ = 1U,
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HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
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} HAL_TickFreqTypeDef;
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/**
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* @}
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*/
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#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
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/** @defgroup HAL_Pin_remapping HAL Pin remapping
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* @{
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*/
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#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
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0: No remap (pin pair PA9/10 mapped on the pins)
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1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
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/**
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* @}
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*/
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#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
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#if defined(STM32F091xC) || defined(STM32F098xx)
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/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
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* @note Applicable on STM32F09x
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* @{
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*/
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#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
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#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
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#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
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/**
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* @}
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*/
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#endif /* STM32F091xC || STM32F098xx */
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/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
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* @{
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*/
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/** @brief Fast-mode Plus driving capability on a specific GPIO
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*/
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#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
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defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
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defined(STM32F070xB) || defined(STM32F030x6)
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#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
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#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
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#endif
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#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
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#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
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#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
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#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
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/**
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* @}
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*/
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#if defined(STM32F091xC) || defined (STM32F098xx)
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/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
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* @brief ISR Wrapper
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* @note applicable on STM32F09x
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* @{
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*/
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#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */
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#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */
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#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
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#if defined(STM32F091xC)
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#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
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#endif
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#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
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#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
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#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
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#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
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#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
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#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
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#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
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#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
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#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
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#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
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#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
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#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
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#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
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#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
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#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
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#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
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#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
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#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
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#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
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#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
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#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
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#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
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#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
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#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
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#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
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#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
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#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
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#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
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#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
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#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
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#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
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#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
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#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
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#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
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#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
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#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
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#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
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#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
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#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
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#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
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#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
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#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
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#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
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#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
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#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
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#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
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#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
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#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
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#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
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#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
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#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
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#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
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#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
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#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
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#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
|
||||
#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
|
||||
#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
|
||||
#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
|
||||
#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
|
||||
#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
|
||||
#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
|
||||
#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
|
||||
#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
|
||||
#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
|
||||
#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
|
||||
#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
|
||||
#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
|
||||
#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
|
||||
* @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
|
||||
#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
|
||||
|
||||
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
|
||||
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
|
||||
* @{
|
||||
*/
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE)
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0)
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
|
||||
|
||||
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
|
||||
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
|
||||
/** @defgroup HAL_Pin_remap HAL Pin remap
|
||||
* @brief Pin remapping enable/disable macros
|
||||
* @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
|
||||
SYSCFG->CFGR1 |= (__PIN_REMAP__); \
|
||||
}while(0)
|
||||
#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
|
||||
SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
|
||||
|
||||
/** @brief Fast-mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
|
||||
* That you can find above these macros.
|
||||
*/
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||
}while(0)
|
||||
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
|
||||
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break Lockup lock
|
||||
* Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_PVD_LOCK)
|
||||
/** @defgroup PVD_Lock_Enable PVD Lock
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break PVD lock
|
||||
* Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_PVD_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
|
||||
/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break SRAM PARITY lock
|
||||
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
|
||||
|
||||
#if defined(SYSCFG_CFGR2_SRAM_PEF)
|
||||
/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
|
||||
* @brief Parity check on RAM disable macro
|
||||
* @note Disabling the parity check on RAM locks the configuration bit.
|
||||
* To re-enable the parity check on RAM perform a system reset.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* SYSCFG_CFGR2_SRAM_PEF */
|
||||
|
||||
|
||||
#if defined(STM32F091xC) || defined (STM32F098xx)
|
||||
/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
|
||||
* @brief ISR wrapper check
|
||||
* @note This feature is applicable on STM32F09x
|
||||
* @note Allow to determine interrupt source per line.
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* (STM32F091xC) || defined (STM32F098xx)*/
|
||||
|
||||
#if defined(STM32F091xC) || defined (STM32F098xx)
|
||||
/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
|
||||
* @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
|
||||
* @note This feature is applicable on STM32F09x
|
||||
* @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
|
||||
* @{
|
||||
*/
|
||||
#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
|
||||
SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
|
||||
SYSCFG->CFGR1 |= (__SOURCE__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* (STM32F091xC) || defined (STM32F098xx)*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
133
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h
Normal file
133
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h
Normal file
@@ -0,0 +1,133 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_CORTEX_H
|
||||
#define __STM32F0xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
|
||||
#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions *************************************************/
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
178
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h
Normal file
178
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h
Normal file
@@ -0,0 +1,178 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_DEF
|
||||
#define __STM32F0xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h"
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
|
||||
|
||||
#if (USE_RTOS == 1U)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0U)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F0xx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
563
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h
Normal file
563
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma.h
Normal file
@@ -0,0 +1,563 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_DMA_H
|
||||
#define __STM32F0xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Callback ID structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
|
||||
}HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
} DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
|
||||
#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
|
||||
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
|
||||
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */
|
||||
#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */
|
||||
#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */
|
||||
#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */
|
||||
#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */
|
||||
#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */
|
||||
#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */
|
||||
#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */
|
||||
#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */
|
||||
#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */
|
||||
#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */
|
||||
#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */
|
||||
#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */
|
||||
#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */
|
||||
#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */
|
||||
#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */
|
||||
#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */
|
||||
#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */
|
||||
#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */
|
||||
#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */
|
||||
#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */
|
||||
#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */
|
||||
#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */
|
||||
#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */
|
||||
#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */
|
||||
#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */
|
||||
#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */
|
||||
#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @defgroup HAL_DMA_remapping HAL DMA remapping
|
||||
* Elements values convention: 0xYYYYYYYY
|
||||
* - YYYYYYYY : Position in the SYSCFG register CFGR1
|
||||
* @{
|
||||
*/
|
||||
#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
|
||||
0: No remap (ADC DMA requests mapped on DMA channel 1
|
||||
1: Remap (ADC DMA requests mapped on DMA channel 2 */
|
||||
#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
|
||||
0: No remap (USART1_TX DMA request mapped on DMA channel 2
|
||||
1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
|
||||
#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
|
||||
0: No remap (USART1_RX DMA request mapped on DMA channel 3
|
||||
1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
|
||||
#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
|
||||
0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
|
||||
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
|
||||
#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
|
||||
0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
|
||||
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
|
||||
#if defined (STM32F070xB)
|
||||
#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
|
||||
0: Disabled, need to remap before use
|
||||
1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
|
||||
|
||||
#endif
|
||||
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
|
||||
#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
|
||||
0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
|
||||
1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
|
||||
#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
|
||||
0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
|
||||
1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
|
||||
#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
|
||||
1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
|
||||
#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
|
||||
1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
|
||||
#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
|
||||
1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
|
||||
#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
|
||||
1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
|
||||
#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
|
||||
1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
|
||||
#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
|
||||
1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
|
||||
#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
|
||||
0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
|
||||
1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__ DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Enables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disables the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
|
||||
* @param __HANDLE__ DMA handle
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
/** @brief DMA remapping enable/disable macros
|
||||
* @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping
|
||||
*/
|
||||
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 |= (__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
|
||||
SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
|
||||
}while(0)
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f0xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Input and Output operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
||||
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
|
||||
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
|
||||
((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
|
||||
((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
|
||||
((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
|
||||
((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
|
||||
((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
|
||||
((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
|
||||
((RMP) == DMA_REMAP_TIM3_DMA_CH6))
|
||||
#elif defined (STM32F070xB)
|
||||
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
|
||||
((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH2))
|
||||
#else
|
||||
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
||||
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
||||
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
||||
((RMP) == DMA_REMAP_TIM17_DMA_CH2))
|
||||
#endif
|
||||
|
||||
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
811
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h
Normal file
811
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_dma_ex.h
Normal file
@@ -0,0 +1,811 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_DMA_EX_H
|
||||
#define __STM32F0xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#if !defined(STM32F030xC)
|
||||
#define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/****************** DMA1 remap bit field definition********************/
|
||||
/* DMA1 - Channel 1 */
|
||||
#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
|
||||
#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
|
||||
#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 2 */
|
||||
#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
|
||||
#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 3 */
|
||||
#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
|
||||
#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 4 */
|
||||
#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
|
||||
#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
/* DMA1 - Channel 5 */
|
||||
#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
|
||||
#if !defined(STM32F030xC)
|
||||
#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
|
||||
#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
#if !defined(STM32F030xC)
|
||||
/* DMA1 - Channel 6 */
|
||||
#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
|
||||
#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
|
||||
/* DMA1 - Channel 7 */
|
||||
#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
|
||||
#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
|
||||
#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
|
||||
|
||||
/****************** DMA2 remap bit field definition********************/
|
||||
/* DMA2 - Channel 1 */
|
||||
#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
|
||||
#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
|
||||
/* DMA2 - Channel 2 */
|
||||
#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
|
||||
#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
|
||||
/* DMA2 - Channel 3 */
|
||||
#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
|
||||
#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
|
||||
/* DMA2 - Channel 4 */
|
||||
#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
|
||||
#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
|
||||
/* DMA2 - Channel 5 */
|
||||
#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
|
||||
#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
|
||||
#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
|
||||
#endif /* !defined(STM32F030xC) */
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH7_USART8_TX))
|
||||
|
||||
#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_ADC) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
|
||||
((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F030xC)
|
||||
#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_ADC) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
|
||||
((REQUEST) == HAL_DMA1_CH5_USART6_RX))
|
||||
#endif /* STM32F030xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
DMA_FLAG_GL7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
|
||||
|
||||
#elif defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
|
||||
DMA_FLAG_GL5)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
|
||||
(DMA1->ISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
|
||||
(DMA1->IFCR = (__FLAG__)))
|
||||
|
||||
#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
DMA_FLAG_TC5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
DMA_FLAG_HT5)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
DMA_FLAG_TE5)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
|
||||
DMA_FLAG_GL5)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_5 to select the DMA Channel flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* Where x can be 1_5 to select the DMA Channel flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define __HAL_DMA1_REMAP(__REQUEST__) \
|
||||
do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
|
||||
DMA1->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
|
||||
DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
|
||||
}while(0)
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
#define __HAL_DMA2_REMAP(__REQUEST__) \
|
||||
do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
|
||||
DMA2->CSELR &= ~(0x0FU << (uint32_t)(((__REQUEST__) >> 28U) * 4U)); \
|
||||
DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
|
||||
}while(0)
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_DMA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
375
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h
Normal file
375
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_exti.h
Normal file
@@ -0,0 +1,375 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_EXTI_H
|
||||
#define STM32F0xx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL EXTI common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
|
||||
|
||||
#if defined (EXTI_IMR_MR16)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#else
|
||||
#define EXTI_LINE_16 (EXTI_RESERVED | 0x10u)
|
||||
#endif /* EXTI_IMR_MR16 */
|
||||
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
|
||||
#if defined (EXTI_IMR_MR18)
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
|
||||
#else
|
||||
#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u)
|
||||
#endif /* EXTI_IMR_MR18 */
|
||||
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
|
||||
#if defined (EXTI_IMR_MR20)
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u)
|
||||
#endif /* EXTI_IMR_MR20 */
|
||||
|
||||
#if defined (EXTI_IMR_MR21)
|
||||
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */
|
||||
#else
|
||||
#define EXTI_LINE_21 (EXTI_RESERVED | 0x15u)
|
||||
#endif /* EXTI_IMR_MR21 */
|
||||
|
||||
#if defined (EXTI_IMR_MR22)
|
||||
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */
|
||||
#else
|
||||
#define EXTI_LINE_22 (EXTI_RESERVED | 0x16u)
|
||||
#endif /* EXTI_IMR_MR22 */
|
||||
|
||||
#if defined (EXTI_IMR_MR23)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | 0x17u) /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_23 (EXTI_RESERVED | 0x17u)
|
||||
#endif /* EXTI_IMR_MR23 */
|
||||
|
||||
#define EXTI_LINE_24 (EXTI_RESERVED | 0x18u)
|
||||
|
||||
#if defined (EXTI_IMR_MR25)
|
||||
#define EXTI_LINE_25 (EXTI_CONFIG | 0x19u) /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_25 (EXTI_RESERVED | 0x19u)
|
||||
#endif /* EXTI_IMR_MR25 */
|
||||
|
||||
#if defined (EXTI_IMR_MR26)
|
||||
#define EXTI_LINE_26 (EXTI_CONFIG | 0x1Au) /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_26 (EXTI_RESERVED | 0x1Au)
|
||||
#endif /* EXTI_IMR_MR26 */
|
||||
|
||||
#if defined (EXTI_IMR_MR27)
|
||||
#define EXTI_LINE_27 (EXTI_CONFIG | 0x1Bu) /*!< External interrupt line 27 Connected to the internal CEC wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_27 (EXTI_RESERVED | 0x1Bu)
|
||||
#endif /* EXTI_IMR_MR27 */
|
||||
|
||||
#if defined (EXTI_IMR_MR28)
|
||||
#define EXTI_LINE_28 (EXTI_CONFIG | 0x1Cu) /*!< External interrupt line 28 Connected to the internal USART3 wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_28 (EXTI_RESERVED | 0x1Cu)
|
||||
#endif /* EXTI_IMR_MR28 */
|
||||
|
||||
#define EXTI_LINE_29 (EXTI_RESERVED | 0x1Du)
|
||||
#define EXTI_LINE_30 (EXTI_RESERVED | 0x1Eu)
|
||||
|
||||
#if defined (EXTI_IMR_MR31)
|
||||
#define EXTI_LINE_31 (EXTI_CONFIG | 0x1Fu) /*!< External interrupt line 31 Connected to the VDDIO2 supply comparator output */
|
||||
#else
|
||||
#define EXTI_LINE_31 (EXTI_RESERVED | 0x1Fu)
|
||||
#endif /* EXTI_IMR_MR31 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000u
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||
#define EXTI_MODE_EVENT 0x00000002u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#if defined (GPIOD)
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#endif /* GPIOD */
|
||||
#if defined (GPIOE)
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#endif /* GPIOE */
|
||||
#define EXTI_GPIOF 0x00000005u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24u
|
||||
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI bit usage
|
||||
*/
|
||||
#define EXTI_PIN_MASK 0x0000001Fu
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#define EXTI_LINE_NB 32uL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#if defined (GPIOE)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#elif defined (GPIOD)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#else
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOF))
|
||||
#endif /* GPIOE */
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
353
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h
Normal file
353
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h
Normal file
@@ -0,0 +1,353 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Flash HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_FLASH_H
|
||||
#define __STM32F0xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
||||
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
|
||||
((__LATENCY__) == FLASH_LATENCY_1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_PAGEERASE = 1U,
|
||||
FLASH_PROC_MASSERASE = 2U,
|
||||
FLASH_PROC_PROGRAMHALFWORD = 3U,
|
||||
FLASH_PROC_PROGRAMWORD = 4U,
|
||||
FLASH_PROC_PROGRAMDOUBLEWORD = 5U
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
|
||||
|
||||
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
|
||||
|
||||
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< FLASH locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< FLASH error code
|
||||
This parameter can be a value of @ref FLASH_Error_Codes */
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Codes FLASH Error Codes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
|
||||
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U) /*!<Program a double word (64-bit) at a specified address*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_Flag_definition FLASH Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_EM_Latency FLASH Latency
|
||||
* @brief macros to handle FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Prefetch FLASH Prefetch
|
||||
* @brief macros to handle FLASH Prefetch buffer
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_ERR Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
|
||||
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */
|
||||
#include "stm32f0xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
|
||||
/* FLASH IRQ handler function */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function -------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
448
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h
Normal file
448
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash_ex.h
Normal file
@@ -0,0 +1,448 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Flash HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_FLASH_EX_H
|
||||
#define __STM32F0xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
|
||||
|
||||
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1))/*||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))*/
|
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET))
|
||||
#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
|
||||
#endif /* FLASH_OBR_BOOT_SEL */
|
||||
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
|
||||
|
||||
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END)
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */
|
||||
|
||||
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
|
||||
This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
|
||||
|
||||
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
|
||||
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Options bytes program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_OB_Type */
|
||||
|
||||
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_OB_WRP_State */
|
||||
|
||||
uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
|
||||
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
|
||||
|
||||
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
|
||||
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
|
||||
|
||||
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
|
||||
IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY
|
||||
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
|
||||
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and
|
||||
@ref FLASHEx_OB_RAM_Parity_Check_Enable */
|
||||
|
||||
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
|
||||
This parameter can be a value of @ref FLASHEx_OB_Data_Address */
|
||||
|
||||
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|
||||
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
|
||||
#define FLASH_PAGE_SIZE 0x400U
|
||||
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define FLASH_PAGE_SIZE 0x800U
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Pages erase only*/
|
||||
#define FLASH_TYPEERASE_MASSERASE (0x01U) /*!<Flash mass erase activation*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Type Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
|
||||
#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
|
||||
#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
|
||||
#define OPTIONBYTE_DATA (0x08U) /*!<DATA option byte configuration*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired pages*/
|
||||
#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired pagess*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|
||||
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
|
||||
#define OB_WRP_PAGES0TO3 (0x00000001U) /* Write protection of page 0 to 3 */
|
||||
#define OB_WRP_PAGES4TO7 (0x00000002U) /* Write protection of page 4 to 7 */
|
||||
#define OB_WRP_PAGES8TO11 (0x00000004U) /* Write protection of page 8 to 11 */
|
||||
#define OB_WRP_PAGES12TO15 (0x00000008U) /* Write protection of page 12 to 15 */
|
||||
#define OB_WRP_PAGES16TO19 (0x00000010U) /* Write protection of page 16 to 19 */
|
||||
#define OB_WRP_PAGES20TO23 (0x00000020U) /* Write protection of page 20 to 23 */
|
||||
#define OB_WRP_PAGES24TO27 (0x00000040U) /* Write protection of page 24 to 27 */
|
||||
#define OB_WRP_PAGES28TO31 (0x00000080U) /* Write protection of page 28 to 31 */
|
||||
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
|
||||
#define OB_WRP_PAGES32TO35 (0x00000100U) /* Write protection of page 32 to 35 */
|
||||
#define OB_WRP_PAGES36TO39 (0x00000200U) /* Write protection of page 36 to 39 */
|
||||
#define OB_WRP_PAGES40TO43 (0x00000400U) /* Write protection of page 40 to 43 */
|
||||
#define OB_WRP_PAGES44TO47 (0x00000800U) /* Write protection of page 44 to 47 */
|
||||
#define OB_WRP_PAGES48TO51 (0x00001000U) /* Write protection of page 48 to 51 */
|
||||
#define OB_WRP_PAGES52TO57 (0x00002000U) /* Write protection of page 52 to 57 */
|
||||
#define OB_WRP_PAGES56TO59 (0x00004000U) /* Write protection of page 56 to 59 */
|
||||
#define OB_WRP_PAGES60TO63 (0x00008000U) /* Write protection of page 60 to 63 */
|
||||
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
|
||||
|
||||
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|
||||
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
|
||||
#define OB_WRP_PAGES0TO31MASK (0x000000FFU)
|
||||
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
|
||||
#define OB_WRP_PAGES32TO63MASK (0x0000FF00U)
|
||||
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
|
||||
|
||||
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
|
||||
#define OB_WRP_ALLPAGES (0x000000FFU) /*!< Write protection of all pages */
|
||||
#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
|
||||
#define OB_WRP_ALLPAGES (0x0000FFFFU) /*!< Write protection of all pages */
|
||||
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
|
||||
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
|
||||
#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
|
||||
#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
|
||||
#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
|
||||
#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
|
||||
#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
|
||||
#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
|
||||
#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
|
||||
#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
|
||||
#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
|
||||
#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
|
||||
#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
|
||||
#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
|
||||
#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
|
||||
#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
|
||||
#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
|
||||
#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
|
||||
#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
|
||||
#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
|
||||
#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
|
||||
#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
|
||||
#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
|
||||
#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
|
||||
#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
|
||||
#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
|
||||
#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
|
||||
#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
|
||||
#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
|
||||
#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
|
||||
#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
|
||||
#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
|
||||
#define OB_WRP_PAGES62TO63 (0x80000000U) /* Write protection of page 62 to 63 */
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES0TO15MASK (0x000000FFU)
|
||||
#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
|
||||
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
|
||||
#define OB_WRP_PAGES48TO63MASK (0xFF000000U)
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
|
||||
#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
|
||||
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
|
||||
|
||||
#define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*!< Write protection of all pages */
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
|
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint8_t)0x01U) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00U) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10U) /*!< BOOT1 Set */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
|
||||
* @{
|
||||
*/
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*!< SRAM parity check enable set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
/** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx Option Byte BOOT SEL
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT_SEL_RESET ((uint8_t)0x00U) /*!< BOOT_SEL Reset */
|
||||
#define OB_BOOT_SEL_SET ((uint8_t)0x80U) /*!< BOOT_SEL Set */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_OB_BOOT0 FLASHEx Option Byte BOOT0
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT0_RESET ((uint8_t)0x00U) /*!< BOOT0 Reset */
|
||||
#define OB_BOOT0_SET ((uint8_t)0x08U) /*!< BOOT0 Set */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OBR_BOOT_SEL */
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
|
||||
* @{
|
||||
*/
|
||||
#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
|
||||
#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
322
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h
Normal file
322
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio.h
Normal file
@@ -0,0 +1,322 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_GPIO_H
|
||||
#define __STM32F0xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection *//**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed GPIO speed
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull GPIO pull
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_Pos 0U
|
||||
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4U
|
||||
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16U
|
||||
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20U
|
||||
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
||||
((__PULL__) == GPIO_PULLUP) || \
|
||||
((__PULL__) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extended module */
|
||||
#include "stm32f0xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
800
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h
Normal file
800
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_gpio_ex.h
Normal file
@@ -0,0 +1,800 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_GPIO_EX_H
|
||||
#define __STM32F0xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F030x6)
|
||||
/*------------------------- STM32F030x6---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F030x6 */
|
||||
|
||||
/*---------------------------------- STM32F030x8 -------------------------------------------*/
|
||||
#if defined (STM32F030x8)
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F030x8 */
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F038xx)
|
||||
/*--------------------------- STM32F031x6/STM32F038xx ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDAT ((uint8_t)0x00U) /*!< AF0: SWDAT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F031x6 || STM32F038xx */
|
||||
|
||||
#if defined (STM32F051x8) || defined (STM32F058xx)
|
||||
/*--------------------------- STM32F051x8/STM32F058xx---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F051x8/STM32F058xx */
|
||||
|
||||
#if defined (STM32F071xB)
|
||||
/*--------------------------- STM32F071xB ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: AEVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F071xB */
|
||||
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*--------------------------- STM32F091xC || STM32F098xx ------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART8 ((uint8_t)0x00U) /*!< AF0: USART8 Alternate Function mapping */
|
||||
#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART4 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART5 ((uint8_t)0x01U) /*!< AF1: USART5 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART6 ((uint8_t)0x01U) /*!< AF1: USART6 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART7 ((uint8_t)0x01U) /*!< AF1: USART7 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART8 ((uint8_t)0x01U) /*!< AF1: USART8 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: TSC Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART7 ((uint8_t)0x02U) /*!< AF2: USART7 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART8 ((uint8_t)0x02U) /*!< AF2: USART8 Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F030xC)
|
||||
/*--------------------------- STM32F030xC ----------------------------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USART5 ((uint8_t)0x02U) /*!< AF2: USART5 Alternate Function mapping */
|
||||
#define GPIO_AF2_USART6 ((uint8_t)0x02U) /*!< AF2: USART6 Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART5 ((uint8_t)0x04U) /*!< AF4: USART5 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_USART6 ((uint8_t)0x05U) /*!< AF5: USART6 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F030xC */
|
||||
|
||||
#if defined (STM32F072xB) || defined (STM32F078xx)
|
||||
/*--------------------------- STM32F072xB/STM32F078xx ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM1 ((uint8_t)0x00U) /*!< AF0: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM16 ((uint8_t)0x00U) /*!< AF0: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_TSC ((uint8_t)0x00U) /*!< AF0: TSC Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART2 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART3 ((uint8_t)0x00U) /*!< AF0: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF0_CAN ((uint8_t)0x00U) /*!< AF0: CAN Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TSC ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI1 ((uint8_t)0x01U) /*!< AF1: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
/* AF 7 */
|
||||
#define GPIO_AF7_COMP1 ((uint8_t)0x07U) /*!< AF7: COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF7_COMP2 ((uint8_t)0x07U) /*!< AF7: COMP2 Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07U)
|
||||
|
||||
#endif /* STM32F072xB || STM32F078xx */
|
||||
|
||||
#if defined (STM32F070xB)
|
||||
/*---------------------------------- STM32F070xB ---------------------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM3 ((uint8_t)0x00U) /*!< AF0: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM15 ((uint8_t)0x00U) /*!< AF0: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART4 ((uint8_t)0x00U) /*!< AF0: USART4 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /*!< AF1: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART3 ((uint8_t)0x01U) /*!< AF1: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C2 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_SPI2 ((uint8_t)0x01U) /*!< AF1: SPI2 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /*!< AF3: TIM15 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART4 ((uint8_t)0x04U) /*!< AF4: USART4 Alternate Function mapping */
|
||||
#define GPIO_AF4_USART3 ((uint8_t)0x04U) /*!< AF4: USART3 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_TIM15 ((uint8_t)0x05U) /*!< AF5: TIM15 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F070xB */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx)
|
||||
/*--------------------------- STM32F042x6/STM32F048xx ---------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_CEC ((uint8_t)0x00U) /*!< AF0: CEC Alternate Function mapping */
|
||||
#define GPIO_AF0_CRS ((uint8_t)0x00U) /*!< AF0: CRS Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1/I2S1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI2 ((uint8_t)0x00U) /*!< AF0: SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_CEC ((uint8_t)0x01U) /*!< AF1: CEC Alternate Function mapping */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /*!< AF2: TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF3_TSC ((uint8_t)0x03U) /*!< AF3: TSC Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_CAN ((uint8_t)0x04U) /*!< AF4: CAN Alternate Function mapping */
|
||||
#define GPIO_AF4_CRS ((uint8_t)0x04U) /*!< AF4: CRS Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C2 ((uint8_t)0x05U) /*!< AF5: I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /*!< AF5: SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F042x6 || STM32F048xx */
|
||||
|
||||
#if defined (STM32F070x6)
|
||||
/*--------------------------------------- STM32F070x6 ----------------------------------------*/
|
||||
/* AF 0 */
|
||||
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00U) /*!< AF0: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_IR ((uint8_t)0x00U) /*!< AF0: IR Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /*!< AF0: MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_SPI1 ((uint8_t)0x00U) /*!< AF0: SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF0_SWDIO ((uint8_t)0x00U) /*!< AF0: SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_SWCLK ((uint8_t)0x00U) /*!< AF0: SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM14 ((uint8_t)0x00U) /*!< AF0: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF0_TIM17 ((uint8_t)0x00U) /*!< AF0: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF0_USART1 ((uint8_t)0x00U) /*!< AF0: USART1 Alternate Function mapping */
|
||||
|
||||
/* AF 1 */
|
||||
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /*!< AF1: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C1 ((uint8_t)0x01U) /*!< AF1: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF1_IR ((uint8_t)0x01U) /*!< AF1: IR Alternate Function mapping */
|
||||
#define GPIO_AF1_USART1 ((uint8_t)0x01U) /*!< AF1: USART1 Alternate Function mapping */
|
||||
#define GPIO_AF1_USART2 ((uint8_t)0x01U) /*!< AF1: USART2 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM3 ((uint8_t)0x01U) /*!< AF1: TIM3 Alternate Function mapping */
|
||||
|
||||
/* AF 2 */
|
||||
#define GPIO_AF2_EVENTOUT ((uint8_t)0x02U) /*!< AF2: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /*!< AF2: TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /*!< AF2: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM17 ((uint8_t)0x02U) /*!< AF2: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF2_USB ((uint8_t)0x02U) /*!< AF2: USB Alternate Function mapping */
|
||||
|
||||
/* AF 3 */
|
||||
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03U) /*!< AF3: EVENTOUT Alternate Function mapping */
|
||||
#define GPIO_AF3_I2C1 ((uint8_t)0x03U) /*!< AF3: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 4 */
|
||||
#define GPIO_AF4_TIM14 ((uint8_t)0x04U) /*!< AF4: TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /*!< AF4: I2C1 Alternate Function mapping */
|
||||
|
||||
/* AF 5 */
|
||||
#define GPIO_AF5_MCO ((uint8_t)0x05U) /*!< AF5: MCO Alternate Function mapping */
|
||||
#define GPIO_AF5_I2C1 ((uint8_t)0x05U) /*!< AF5: I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM16 ((uint8_t)0x05U) /*!< AF5: TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF5_TIM17 ((uint8_t)0x05U) /*!< AF5: TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF5_USB ((uint8_t)0x05U) /*!< AF5: USB Alternate Function mapping */
|
||||
|
||||
/* AF 6 */
|
||||
#define GPIO_AF6_EVENTOUT ((uint8_t)0x06U) /*!< AF6: EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x06U)
|
||||
|
||||
#endif /* STM32F070x6 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#if defined(GPIOD) && defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U : 5U)
|
||||
#endif
|
||||
|
||||
#if defined(GPIOD) && !defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U : 5U)
|
||||
#endif
|
||||
|
||||
#if !defined(GPIOD) && defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U : 5U)
|
||||
#endif
|
||||
|
||||
#if !defined(GPIOD) && !defined(GPIOE)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U : 5U)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
838
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h
Normal file
838
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c.h
Normal file
@@ -0,0 +1,838 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_I2C_H
|
||||
#define STM32F0xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32f0xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f0xx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F0xx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
193
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h
Normal file
193
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h
Normal file
@@ -0,0 +1,193 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_I2C_EX_H
|
||||
#define STM32F0xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
|
||||
#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */
|
||||
#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */
|
||||
#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */
|
||||
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */
|
||||
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
|
||||
#endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c,
|
||||
uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c,
|
||||
uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(I2C_CR1_WUPEN)
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* I2C_CR1_WUPEN */
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
|
||||
((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_I2C_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
189
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h
Normal file
189
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h
Normal file
@@ -0,0 +1,189 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_PWR_H
|
||||
#define __STM32F0xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON (0x00000000U)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macro PWR Exported Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received from the WKUP pin or from the RTC alarm (Alarm A),
|
||||
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
|
||||
* An additional wakeup event is detected if the WKUP pin is enabled
|
||||
* (by setting the EWUP bit) when the WKUP pin level is already high.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* Warning: this Flag is not available on STM32F030x8 products
|
||||
* @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
|
||||
* voltage VREFINT is ready.
|
||||
* Warning: this Flag is not available on STM32F030x8 products
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extension module */
|
||||
#include "stm32f0xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F0xx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
459
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
Normal file
459
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr_ex.h
Normal file
@@ -0,0 +1,459 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0xx_HAL_PWR_EX_H
|
||||
#define __STM32F0xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Types PWREx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
|
||||
This parameter can be a value of @ref PWREx_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
|
||||
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
|
||||
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
|
||||
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
|
||||
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
|
||||
#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8)
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6) || \
|
||||
((PIN) == PWR_WAKEUP_PIN7) || \
|
||||
((PIN) == PWR_WAKEUP_PIN8))
|
||||
|
||||
#elif defined(STM32F030xC) || defined (STM32F070xB)
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
|
||||
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
|
||||
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
|
||||
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6) || \
|
||||
((PIN) == PWR_WAKEUP_PIN7))
|
||||
|
||||
#elif defined(STM32F042x6) || defined (STM32F048xx)
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
|
||||
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
|
||||
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4) || \
|
||||
((PIN) == PWR_WAKEUP_PIN6) || \
|
||||
((PIN) == PWR_WAKEUP_PIN7))
|
||||
|
||||
#else
|
||||
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
|
||||
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_EXTI_Line PWREx EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
|
||||
#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
|
||||
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) ||*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVD_Mode PWREx PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
/** @defgroup PWREx_Flag PWREx Flag
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
#else
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macros PWREx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
/**
|
||||
* @brief Enable interrupt on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/**
|
||||
* @brief Enable interrupt on Vddio2 Monitor Exti Line 31.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on Vddio2 Monitor Exti Line 31.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \
|
||||
do{ \
|
||||
EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
|
||||
EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
|
||||
* @retval EXTI VDDIO2 Monitor Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Clear the VDDIO2 Monitor EXTI flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2))
|
||||
|
||||
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
void HAL_PWREx_Vddio2Monitor_IRQHandler(void);
|
||||
void HAL_PWREx_Vddio2MonitorCallback(void);
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || \
|
||||
defined (STM32F091xC)
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F072xB) || */
|
||||
/* defined (STM32F091xC) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
void HAL_PWREx_EnableVddio2Monitor(void);
|
||||
void HAL_PWREx_DisableVddio2Monitor(void);
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0xx_HAL_PWR_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
1686
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h
Normal file
1686
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc.h
Normal file
File diff suppressed because it is too large
Load Diff
2085
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h
Normal file
2085
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_rcc_ex.h
Normal file
File diff suppressed because it is too large
Load Diff
2131
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h
Normal file
2131
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h
Normal file
File diff suppressed because it is too large
Load Diff
268
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h
Normal file
268
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h
Normal file
@@ -0,0 +1,268 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TIM HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_TIM_EX_H
|
||||
#define STM32F0xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
|
||||
#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
|
||||
#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
|
||||
#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macro -----------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
|
||||
(((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macro ------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||
* @brief Timer Hall Sensor functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||
* @brief Timer Complementary Output Compare functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||
* @brief Timer Complementary PWM functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||
* @brief Timer Complementary One Pulse functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||
* @brief Extended Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Callback **********************************************************/
|
||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||
* @brief Extended Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F0xx_HAL_TIM_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1633
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h
Normal file
1633
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart.h
Normal file
File diff suppressed because it is too large
Load Diff
592
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h
Normal file
592
Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_uart_ex.h
Normal file
@@ -0,0 +1,592 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_uart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UART HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F0xx_HAL_UART_EX_H
|
||||
#define STM32F0xx_HAL_UART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
/**
|
||||
* @brief UART wake up from stop mode parameters
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
|
||||
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
|
||||
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
|
||||
be filled up. */
|
||||
|
||||
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
|
||||
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
|
||||
|
||||
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
|
||||
} UART_WakeUpTypeDef;
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Word_Length UARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_M1)
|
||||
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
|
||||
#endif /* USART_CR1_M1 */
|
||||
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
|
||||
#if defined (USART_CR1_M0)
|
||||
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
|
||||
#else
|
||||
#define UART_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long UART frame */
|
||||
#endif /* USART_CR1_M0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
|
||||
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UARTEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
|
||||
uint32_t DeassertionTime);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
#if defined(USART_CR1_UESM)
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif/* USART_CR1_UESM */
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the UART clock source.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval UART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
|
||||
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F070xB)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F091xC) || defined (STM32F098xx)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART7) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART8) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
#elif defined(STM32F030xC)
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART4) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART5) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
|
||||
|
||||
/** @brief Report the UART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#if defined (USART_CR1_M1)
|
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
#else
|
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
#endif /* USART_CR1_M1 */
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART frame length is valid.
|
||||
* @param __LENGTH__ UART frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#if defined (USART_CR1_M1)
|
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B))
|
||||
#else
|
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B))
|
||||
#endif /* USART_CR1_M1 */
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART wake-up address length is valid.
|
||||
* @param __ADDRESS__ UART wake-up address length.
|
||||
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
|
||||
*/
|
||||
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
|
||||
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F0xx_HAL_UART_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
514
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c
Normal file
514
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal.c
Normal file
@@ -0,0 +1,514 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs categories:
|
||||
(+) HAL Initialization and de-initialization functions
|
||||
(+) HAL Control functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @brief HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F0xx HAL Driver version number V1.7.6
|
||||
*/
|
||||
#define __STM32F0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32F0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
|
||||
|(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\
|
||||
|(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\
|
||||
|(__STM32F0xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK (0x00000FFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Variables HAL Exported Variables
|
||||
* @{
|
||||
*/
|
||||
__IO uint32_t uwTick;
|
||||
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
|
||||
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initializes the Flash interface, the NVIC allocation and initial clock
|
||||
configuration. It initializes the systick also when timeout is needed
|
||||
and the backup domain when enabled.
|
||||
(+) de-Initializes common part of the HAL.
|
||||
(+) Configure The time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) SysTick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __Weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Flash prefetch,
|
||||
* Configures time base source, NVIC and Low level hardware
|
||||
* @note This function is called at the beginning of program after reset and before
|
||||
* the clock configuration
|
||||
* @note The time base configuration is based on HSI clock when exiting from Reset.
|
||||
* Once done, time base tick start incrementing.
|
||||
* In the default implementation,Systick is used as source of time base.
|
||||
* The tick variable is incremented each 1ms in its ISR.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
/* Configure Flash prefetch */
|
||||
#if (PREFETCH_ENABLE != 0)
|
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
||||
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initialize common part of the HAL and stops the SysTick
|
||||
* of time base.
|
||||
* @note This function is optional.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__HAL_RCC_APB1_FORCE_RESET();
|
||||
__HAL_RCC_APB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET();
|
||||
__HAL_RCC_APB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB_FORCE_RESET();
|
||||
__HAL_RCC_AHB_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __Weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SysTick IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Provide a tick value in millisecond
|
||||
(+) Provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device identifier
|
||||
(+) Get the device revision identifier
|
||||
(+) Enable/Disable Debug module during Sleep mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in SysTick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick += uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns a tick priority.
|
||||
* @retval tick priority
|
||||
*/
|
||||
uint32_t HAL_GetTickPrio(void)
|
||||
{
|
||||
return uwTickPrio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set new tick Freq.
|
||||
* @retval status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_TickFreqTypeDef prevTickFreq;
|
||||
|
||||
assert_param(IS_TICKFREQ(Freq));
|
||||
|
||||
if (uwTickFreq != Freq)
|
||||
{
|
||||
/* Back up uwTickFreq frequency */
|
||||
prevTickFreq = uwTickFreq;
|
||||
|
||||
/* Update uwTickFreq global variable used by HAL_InitTick() */
|
||||
uwTickFreq = Freq;
|
||||
|
||||
/* Apply the new tick Freq */
|
||||
status = HAL_InitTick(uwTickPrio);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Restore previous tick frequency */
|
||||
uwTickFreq = prevTickFreq;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return tick frequency.
|
||||
* @retval tick period in Hz
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
return uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides accurate delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note ThiS function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a freq to guarantee minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += (uint32_t)(uwTickFreq);
|
||||
}
|
||||
|
||||
while((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This method returns the HAL revision
|
||||
* @retval version 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F0xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)UID_BASE)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
341
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c
Normal file
341
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c
Normal file
@@ -0,0 +1,341 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M0 exceptions are managed by CMSIS functions.
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
The priority can be 0..3.
|
||||
|
||||
-@- Lower priority values gives higher priority.
|
||||
-@- Priority Order:
|
||||
(#@) Lowest priority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
-@- Negative value of IRQn_Type are not allowed.
|
||||
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x03).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
|
||||
inside the stm32f0xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number .
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file)
|
||||
* @param PreemptPriority The preemption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 3.
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
|
||||
* no subpriority supported in Cortex M0 based products.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
NVIC_SetPriority(IRQn,PreemptPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
return NVIC_GetPriority(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
901
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c
Normal file
901
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_dma.c
Normal file
@@ -0,0 +1,901 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary). Please refer to Reference manual for connection between peripherals
|
||||
and DMA requests .
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Transfer Direction, Source and Destination data formats,
|
||||
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
|
||||
using HAL_DMA_Init() function.
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred.
|
||||
In this case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function by customization of function pointer XferCpltCallback and
|
||||
XferErrorCallback (i.e a member of DMA handle structure).
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of most used macros in DMA HAL driver.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Channel source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and initialize the associated handle.
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp = 0U;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if(NULL == hdma)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CCR;
|
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
|
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
||||
DMA_CCR_DIR));
|
||||
|
||||
/* Prepare the DMA Channel configuration */
|
||||
tmp |= hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* Write to DMA Channel CR register */
|
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Initialize DmaBaseAddress and ChannelIndex parameters used
|
||||
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
|
||||
DMA_CalcBaseAndBitshift(hdma);
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdma->Lock = HAL_UNLOCKED;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the DMA peripheral
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the DMA handle allocation */
|
||||
if(NULL == hdma)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Reset DMA Channel control register */
|
||||
hdma->Instance->CCR = 0U;
|
||||
|
||||
/* Reset DMA Channel Number of Data to Transfer register */
|
||||
hdma->Instance->CNDTR = 0U;
|
||||
|
||||
/* Reset DMA Channel peripheral address register */
|
||||
hdma->Instance->CPAR = 0U;
|
||||
|
||||
/* Reset DMA Channel memory address register */
|
||||
hdma->Instance->CMAR = 0U;
|
||||
|
||||
/* Get DMA Base Address */
|
||||
DMA_CalcBaseAndBitshift(hdma);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Clean callbacks */
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
|
||||
/* Reset the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Reset the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief I/O operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
hdma->Instance->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete, & transfer error interrupts */
|
||||
/* Half transfer interrupt is optional: enable it only if associated callback is available */
|
||||
if(NULL != hdma->XferHalfCpltCallback )
|
||||
{
|
||||
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
}
|
||||
else
|
||||
{
|
||||
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
|
||||
hdma->Instance->CCR &= ~DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
hdma->Instance->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
if(hdma->State != HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable DMA IT */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Disable the channel */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
|
||||
}
|
||||
/* Change the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer in Interrupt mode.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
/* Disable DMA IT */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Disable the channel */
|
||||
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Call User Abort callback */
|
||||
if(hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
hdma->XferAbortCallback(hdma);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CompleteLevel Specifies the DMA level complete.
|
||||
* @param Timeout Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
__HAL_UNLOCK(hdma);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Polling mode not supported in circular mode */
|
||||
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
}
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(RESET == (hdma->DmaBaseAddress->ISR & temp))
|
||||
{
|
||||
if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State= HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle DMA interrupt request.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
||||
uint32_t source_it = hdma->Instance->CCR;
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
hdma->Instance->CCR &= ~DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* State is updated only in Transfer Complete case */
|
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
|
||||
{
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the transfer complete & transfer error interrupts */
|
||||
/* if the DMA mode is not CIRCULAR */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Error Interrupt management ***************************************/
|
||||
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Then, disable all DMA interrupts */
|
||||
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifer
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @param pCallback pointer to private callback function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = pCallback;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param CallbackID User Callback identifer
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ALL_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the DMA state.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the DMA Transfer parameters.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
|
||||
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Memory to Peripheral */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CMAR = SrcAddress;
|
||||
}
|
||||
/* Peripheral to Memory */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CMAR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the DMA base address and channel index depending on DMA instance
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @retval None
|
||||
*/
|
||||
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
#if defined (DMA2)
|
||||
/* calculation of the channel index */
|
||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
||||
{
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMA2 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA2;
|
||||
}
|
||||
#else
|
||||
/* calculation of the channel index */
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
549
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c
Normal file
549
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_exti.c
Normal file
@@ -0,0 +1,549 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each Exti line can be configured within this driver.
|
||||
|
||||
(+) Exti line can be configured in 3 different modes
|
||||
(++) Interrupt
|
||||
(++) Event
|
||||
(++) Both of them
|
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||
(++) Rising
|
||||
(++) Falling
|
||||
(++) Both of them
|
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||
interrupts pending registers which allow to distinguish which transition
|
||||
occurs:
|
||||
(++) Rising edge pending interrupt
|
||||
(++) Falling
|
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||
be selected through multiplexer.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||
(++) Choose the interrupt line number by setting "Line" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) For configurable lines, configure rising and/or falling trigger
|
||||
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||
member from GPIO_InitTypeDef structure.
|
||||
|
||||
(#) Get current Exti configuration of a dedicated line using
|
||||
HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
(++) Provide exiting handle as first parameter.
|
||||
(++) Provide which callback will be registered using one value from
|
||||
EXTI_CallbackIDTypeDef.
|
||||
(++) Provide callback function pointer.
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||
* of bounds [0,3] in following API :
|
||||
* HAL_EXTI_SetConfigLine
|
||||
* HAL_EXTI_GetConfigLine
|
||||
* HAL_EXTI_ClearConfigLine
|
||||
*/
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||
|
||||
/* Assign line number to handle */
|
||||
hexti->Line = pExtiConfig->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Configure triggers for configurable lines */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||
|
||||
/* Configure rising trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->RTSR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure falling trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
EXTI->FTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->FTSR &= ~maskline;
|
||||
}
|
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure interrupt mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||
{
|
||||
EXTI->IMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->IMR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure event mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||
{
|
||||
EXTI->EMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->EMR &= ~maskline;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* Store handle line number to configuration structure */
|
||||
pExtiConfig->Line = hexti->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Get core mode : interrupt */
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->IMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Get event mode */
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->EMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* Get default Trigger and GPIOSel configuration */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->RTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->FTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Clear interrupt mode */
|
||||
EXTI->IMR = (EXTI->IMR & ~maskline);
|
||||
|
||||
/* 2] Clear event mode */
|
||||
EXTI->EMR = (EXTI->EMR & ~maskline);
|
||||
|
||||
/* 3] Clear triggers in case of configurable lines */
|
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline);
|
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline);
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param CallbackID User callback identifier.
|
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||
* @param pPendingCbfn function pointer to be stored as callback.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_EXTI_COMMON_CB_ID:
|
||||
hexti->PendingCallback = pPendingCbfn;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field.
|
||||
* @param hexti Exti handle.
|
||||
* @param ExtiLine Exti line number.
|
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store line number as handle private field */
|
||||
hexti->Line = ExtiLine;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param hexti Exti handle.
|
||||
* @retval none.
|
||||
*/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending bit */
|
||||
regval = (EXTI->PR & maskline);
|
||||
if (regval != 0x00u)
|
||||
{
|
||||
/* Clear pending bit */
|
||||
EXTI->PR = maskline;
|
||||
|
||||
/* Call callback */
|
||||
if (hexti->PendingCallback != NULL)
|
||||
{
|
||||
hexti->PendingCallback();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval 1 if interrupt is pending else 0.
|
||||
*/
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* return 1 if bit is set else 0 */
|
||||
regval = ((EXTI->PR & maskline) >> linepos);
|
||||
return regval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Clear Pending bit */
|
||||
EXTI->PR = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Generate Software interrupt */
|
||||
EXTI->SWIER = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
694
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c
Normal file
694
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash.c
Normal file
@@ -0,0 +1,694 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) Option Bytes programming
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F0xx devices.
|
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed
|
||||
functions to erase and program the main memory:
|
||||
(++) Lock and Unlock the FLASH interface
|
||||
(++) Erase function: Erase page, erase all pages
|
||||
(++) Program functions: half word, word and doubleword
|
||||
(#) FLASH Option Bytes Programming functions: this group includes all needed
|
||||
functions to manage the Option Bytes:
|
||||
(++) Lock and Unlock the Option Bytes
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Program the user Option Bytes
|
||||
(++) Launch the Option Bytes loader
|
||||
(++) Erase Option Bytes
|
||||
(++) Program the data Option Bytes
|
||||
(++) Get the Write protection.
|
||||
(++) Get the user option bytes.
|
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to:
|
||||
(++) Handle FLASH interrupts
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status
|
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
|
||||
(+) Set/Get the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro ---------------------------- ---------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
extern void FLASH_PageErase(uint32_t PageAddress);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @note FLASH should be previously erased before new programming (only exception to this
|
||||
* is when 0x0000 is programmed)
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint8_t index = 0U;
|
||||
uint8_t nbiterations = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
nbiterations = 1U;
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
/* Program word (32-bit = 2*16-bit) at a specified address. */
|
||||
nbiterations = 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program double word (64-bit = 4*16-bit) at a specified address. */
|
||||
nbiterations = 4U;
|
||||
}
|
||||
|
||||
for (index = 0U; index < nbiterations; index++)
|
||||
{
|
||||
FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
/* In case of error, stop programming procedure */
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
pFlash.Address = Address;
|
||||
pFlash.Data = Data;
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 1U;
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
|
||||
/* Program word (32-bit : 2*16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 2U;
|
||||
}
|
||||
else
|
||||
{
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
|
||||
/* Program double word (64-bit : 4*16-bit) at a specified address. */
|
||||
pFlash.DataRemaining = 4U;
|
||||
}
|
||||
|
||||
/* Program halfword (16-bit) at a specified address. */
|
||||
FLASH_Program_HalfWord(Address, (uint16_t)Data);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp = 0U;
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/* Return the faulty address */
|
||||
addresstmp = pFlash.Address;
|
||||
/* Reset address */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
|
||||
/* Save the Error code */
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(addresstmp);
|
||||
|
||||
/* Stop the procedure ongoing */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
/* Process can continue only if no error detected */
|
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still pages to erase */
|
||||
if(pFlash.DataRemaining != 0U)
|
||||
{
|
||||
addresstmp = pFlash.Address;
|
||||
/*Indicate user which sector has been erased */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
|
||||
/*Increment sector number*/
|
||||
addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
|
||||
pFlash.Address = addresstmp;
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
FLASH_PageErase(addresstmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more pages to Erase, user callback can be called. */
|
||||
/* Reset Sector and stop Erase pages procedure */
|
||||
pFlash.Address = addresstmp = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
}
|
||||
}
|
||||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
|
||||
{
|
||||
/* Operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
|
||||
/* MassErase ended. Return the selected bank */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(0);
|
||||
|
||||
/* Stop Mass Erase procedure*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nb of 16-bit data to program can be decreased */
|
||||
pFlash.DataRemaining--;
|
||||
|
||||
/* Check if there are still 16-bit data to program */
|
||||
if(pFlash.DataRemaining != 0U)
|
||||
{
|
||||
/* Increment address to 16-bit */
|
||||
pFlash.Address += 2;
|
||||
addresstmp = pFlash.Address;
|
||||
|
||||
/* Shift to have next 16-bit data */
|
||||
pFlash.Data = (pFlash.Data >> 16U);
|
||||
|
||||
/* Operation is completed, disable the PG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Program ended. Return the selected address */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
}
|
||||
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
|
||||
}
|
||||
|
||||
/* Reset Address and stop Program procedure */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Operation is completed, disable the PG, PER and MER Bits */
|
||||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
|
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Mass Erase: No return value expected
|
||||
* - Pages Erase: Address of the page which returned an error
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||
|
||||
/* Verify Flash is unlocked */
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @note This function will reset automatically the MCU.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OBL_Launch bit to launch the option byte loading */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode The returned value can be:
|
||||
* @ref FLASH_Error_Codes
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @param Address specify the address to be programmed.
|
||||
* @param Data specify the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Proceed to program the new data */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
/* Write data in the address */
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operation timeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* There is no error flag set */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0U;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
flags |= FLASH_FLAG_WRPERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
|
||||
flags |= FLASH_FLAG_PGERR;
|
||||
}
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(flags);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
984
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c
Normal file
984
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_flash_ex.c
Normal file
@@ -0,0 +1,984 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the FLASH peripheral:
|
||||
* + Extended Initialization/de-initialization functions
|
||||
* + Extended I/O operation functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flash peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure and program the FLASH memory
|
||||
of all STM32F0xxx devices. It includes
|
||||
|
||||
(++) Set/Reset the write protection
|
||||
(++) Program the user Option Bytes
|
||||
(++) Get the Read protection Level
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx FLASHEx
|
||||
* @brief FLASH HAL Extension module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_POSITION_IWDGSW_BIT 8U
|
||||
#define FLASH_POSITION_OB_USERDATA0_BIT 16U
|
||||
#define FLASH_POSITION_OB_USERDATA1_BIT 24U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Erase operations */
|
||||
static void FLASH_MassErase(void);
|
||||
void FLASH_PageErase(uint32_t PageAddress);
|
||||
|
||||
/* Option bytes control */
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
|
||||
static uint32_t FLASH_OB_GetWRP(void);
|
||||
static uint32_t FLASH_OB_GetRDP(void);
|
||||
static uint8_t FLASH_OB_GetUser(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
|
||||
* @brief FLASH Memory Erasing functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH Erasing Programming functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The FLASH Memory Erasing functions, includes the following functions:
|
||||
(+) HAL_FLASHEx_Erase: return only when erase has been done
|
||||
(+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback
|
||||
is called with parameter 0xFFFFFFFF
|
||||
|
||||
[..] Any operation of erase should follow these steps:
|
||||
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
|
||||
program memory access.
|
||||
(#) Call the desired function to erase page.
|
||||
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
|
||||
(recommended to protect the FLASH memory against possible unwanted operation).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @param[out] PageError pointer to variable that
|
||||
* contains the configuration information on faulty page in case of error
|
||||
* (0xFFFFFFFF means that all the pages have been correctly erased)
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint32_t address = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/* Mass Erase requested for Bank1 */
|
||||
/* Wait for last operation to be completed */
|
||||
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
FLASH_MassErase();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the MER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Page Erase is requested */
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
/* Page Erase requested on address located on bank1 */
|
||||
/* Wait for last operation to be completed */
|
||||
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
|
||||
{
|
||||
/*Initialization of PageError variable*/
|
||||
*PageError = 0xFFFFFFFFU;
|
||||
|
||||
/* Erase page by page to be done*/
|
||||
for(address = pEraseInit->PageAddress;
|
||||
address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
|
||||
address += FLASH_PAGE_SIZE)
|
||||
{
|
||||
FLASH_PageErase(address);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the PER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* In case of error, stop erase procedure and return the faulty address */
|
||||
*PageError = address;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
|
||||
* contains the configuration information for the erasing.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* If procedure already ongoing, reject the next one */
|
||||
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
||||
{
|
||||
/*Mass erase to be done*/
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
|
||||
FLASH_MassErase();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Erase by page to be done*/
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
|
||||
pFlash.DataRemaining = pEraseInit->NbPages;
|
||||
pFlash.Address = pEraseInit->PageAddress;
|
||||
|
||||
/*Erase 1st page and wait for IT*/
|
||||
FLASH_PageErase(pEraseInit->PageAddress);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
|
||||
* @brief Option Bytes Programming functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Option Bytes Programming functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
option bytes operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erases the FLASH option bytes.
|
||||
* @note This functions erases all option bytes except the Read protection (RDP).
|
||||
* The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
|
||||
{
|
||||
uint8_t rdptmp = OB_RDP_LEVEL_0;
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Get the actual read protection Option Byte value */
|
||||
rdptmp = FLASH_OB_GetRDP();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Restore the last read protection Option Byte value */
|
||||
status = FLASH_OB_RDP_LevelConfig(rdptmp);
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program option bytes
|
||||
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
*
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
|
||||
|
||||
/* Write protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
|
||||
{
|
||||
assert_param(IS_WRPSTATE(pOBInit->WRPState));
|
||||
if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
|
||||
{
|
||||
/* Enable of Write protection on the selected page */
|
||||
status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable of Write protection on the selected page */
|
||||
status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
|
||||
}
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Read protection configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
|
||||
{
|
||||
status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* USER configuration */
|
||||
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
|
||||
{
|
||||
status = FLASH_OB_UserConfig(pOBInit->USERConfig);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* DATA configuration*/
|
||||
if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
|
||||
{
|
||||
status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte configuration
|
||||
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
|
||||
* contains the configuration information for the programming.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
|
||||
{
|
||||
pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
|
||||
|
||||
/*Get WRP*/
|
||||
pOBInit->WRPPage = FLASH_OB_GetWRP();
|
||||
|
||||
/*Get RDP Level*/
|
||||
pOBInit->RDPLevel = FLASH_OB_GetRDP();
|
||||
|
||||
/*Get USER*/
|
||||
pOBInit->USERConfig = FLASH_OB_GetUser();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Option byte user data
|
||||
* @param DATAAdress Address of the option byte DATA
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_DATA_ADDRESS_DATA0
|
||||
* @arg @ref OB_DATA_ADDRESS_DATA1
|
||||
* @retval Value programmed in USER data
|
||||
*/
|
||||
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
|
||||
{
|
||||
uint32_t value = 0U;
|
||||
|
||||
if (DATAAdress == OB_DATA_ADDRESS_DATA0)
|
||||
{
|
||||
/* Get value programmed in OB USER Data0 */
|
||||
value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get value programmed in OB USER Data1 */
|
||||
value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Full erase of FLASH memory Bank
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_MassErase(void)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Only bank1 will be erased*/
|
||||
SET_BIT(FLASH->CR, FLASH_CR_MER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection of the desired pages
|
||||
* @note An option byte erase is done automatically in this function.
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage specifies the page(s) to be write protected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFFU;
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
uint16_t WRP1_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
uint16_t WRP2_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
uint16_t WRP3_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
/* Get current write protected pages and the new pages to be protected ******/
|
||||
WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
|
||||
|
||||
#if defined(OB_WRP_PAGES0TO15MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
#elif defined(OB_WRP_PAGES0TO31MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
|
||||
#endif /* OB_WRP_PAGES0TO31MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES16TO31MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
|
||||
#elif defined(OB_WRP_PAGES32TO63MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
|
||||
#endif /* OB_WRP_PAGES32TO63MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES32TO47MASK)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
|
||||
#endif /* OB_WRP_PAGES32TO47MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES48TO63MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U);
|
||||
#elif defined(OB_WRP_PAGES48TO127MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
|
||||
#endif /* OB_WRP_PAGES48TO63MASK */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* To be able to write again option byte, need to perform a option byte erase */
|
||||
status = HAL_FLASHEx_OBErase();
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Enable write protection */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(OB_WRP0_WRP0)
|
||||
if(WRP0_Data != 0xFFU)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP0_WRP0 */
|
||||
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection of the desired pages
|
||||
* @note An option byte erase is done automatically in this function.
|
||||
* @note When the memory read protection level is selected (RDP level = 1),
|
||||
* it is not possible to program or erase the flash page i if
|
||||
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
|
||||
*
|
||||
* @param WriteProtectPage specifies the page(s) to be write unprotected.
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t WRP0_Data = 0xFFFFU;
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
uint16_t WRP1_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
uint16_t WRP2_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
uint16_t WRP3_Data = 0xFFFFU;
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WriteProtectPage));
|
||||
|
||||
/* Get current write protected pages and the new pages to be unprotected ******/
|
||||
WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
|
||||
|
||||
#if defined(OB_WRP_PAGES0TO15MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
|
||||
#elif defined(OB_WRP_PAGES0TO31MASK)
|
||||
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
|
||||
#endif /* OB_WRP_PAGES0TO31MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES16TO31MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
|
||||
#elif defined(OB_WRP_PAGES32TO63MASK)
|
||||
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
|
||||
#endif /* OB_WRP_PAGES32TO63MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES32TO47MASK)
|
||||
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
|
||||
#endif /* OB_WRP_PAGES32TO47MASK */
|
||||
|
||||
#if defined(OB_WRP_PAGES48TO63MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24U);
|
||||
#elif defined(OB_WRP_PAGES48TO127MASK)
|
||||
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
|
||||
#endif /* OB_WRP_PAGES48TO63MASK */
|
||||
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* To be able to write again option byte, need to perform a option byte erase */
|
||||
status = HAL_FLASHEx_OBErase();
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(OB_WRP0_WRP0)
|
||||
if(WRP0_Data != 0xFFU)
|
||||
{
|
||||
OB->WRP0 &= WRP0_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP0_WRP0 */
|
||||
|
||||
#if defined(OB_WRP1_WRP1)
|
||||
if((status == HAL_OK) && (WRP1_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP1 &= WRP1_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP1_WRP1 */
|
||||
|
||||
#if defined(OB_WRP2_WRP2)
|
||||
if((status == HAL_OK) && (WRP2_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP2 &= WRP2_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP2_WRP2 */
|
||||
|
||||
#if defined(OB_WRP3_WRP3)
|
||||
if((status == HAL_OK) && (WRP3_Data != 0xFFU))
|
||||
{
|
||||
OB->WRP3 &= WRP3_Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
#endif /* OB_WRP3_WRP3 */
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the read protection level.
|
||||
* @param ReadProtectLevel specifies the read protection level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_RDP_LEVEL_0 No protection
|
||||
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
|
||||
* @arg @ref OB_RDP_LEVEL_2 Full chip protection
|
||||
* @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the option bytes */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the OPTER Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
WRITE_REG(OB->RDP, ReadProtectLevel);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program the FLASH User Option Byte.
|
||||
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7).
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
|
||||
assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
|
||||
assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
|
||||
assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
|
||||
assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
|
||||
assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET)));
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET)));
|
||||
assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET)));
|
||||
#endif /* FLASH_OBR_BOOT_SEL */
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Enable the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
|
||||
#if defined(FLASH_OBR_BOOT_SEL)
|
||||
OB->USER = UserConfig;
|
||||
#else
|
||||
OB->USER = (UserConfig | 0x88U);
|
||||
#endif
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs a half word at a specified Option Byte Data address.
|
||||
* @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
|
||||
* The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
|
||||
* The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
|
||||
* (system reset will occur)
|
||||
* Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
|
||||
* @param Address specifies the address to be programmed.
|
||||
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
|
||||
* @param Data specifies the data to be programmed.
|
||||
* @retval HAL status
|
||||
*/
|
||||
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_DATA_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Enables the Option Bytes Programming operation */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the OPTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
|
||||
}
|
||||
/* Return the Option Byte Data Program Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH Write Protection Option Bytes value.
|
||||
* @retval The FLASH Write Protection Option Bytes value
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetWRP(void)
|
||||
{
|
||||
/* Return the FLASH write protection Register value */
|
||||
return (uint32_t)(READ_REG(FLASH->WRPR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH Read Protection level.
|
||||
* @retval FLASH RDP level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref OB_RDP_LEVEL_0 No protection
|
||||
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
|
||||
* @arg @ref OB_RDP_LEVEL_2 Full chip protection
|
||||
*/
|
||||
static uint32_t FLASH_OB_GetRDP(void)
|
||||
{
|
||||
uint32_t tmp_reg;
|
||||
|
||||
/* Read RDP level bits */
|
||||
tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2));
|
||||
|
||||
if (tmp_reg == 0U)
|
||||
{
|
||||
return OB_RDP_LEVEL_0;
|
||||
}
|
||||
else if ((tmp_reg & FLASH_OBR_RDPRT2) == FLASH_OBR_RDPRT2)
|
||||
{
|
||||
return OB_RDP_LEVEL_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return OB_RDP_LEVEL_1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the FLASH User Option Byte value.
|
||||
* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
|
||||
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
|
||||
* For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7).
|
||||
*/
|
||||
static uint8_t FLASH_OB_GetUser(void)
|
||||
{
|
||||
/* Return the User Option Byte */
|
||||
return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erase the specified FLASH memory page
|
||||
* @param PageAddress FLASH page to erase
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t PageAddress)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Proceed to erase the page */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PER);
|
||||
WRITE_REG(FLASH->AR, PageAddress);
|
||||
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
540
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c
Normal file
540
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_gpio.c
Normal file
@@ -0,0 +1,540 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(++) Input mode
|
||||
(++) Analog mode
|
||||
(++) Output mode
|
||||
(++) Alternate function mode
|
||||
(++) External interrupt/event lines
|
||||
|
||||
(+) During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
(+) All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
(+) The external interrupt/event controller consists of up to 28 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
|
||||
recommended to use it to unconfigure pin which was used as an external interrupt
|
||||
or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
|
||||
registers.
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** MISRA C:2012 deviation rule has been granted for following rules:
|
||||
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
|
||||
* which may be out of array bounds [..,UNKNOWN] in following APIs:
|
||||
* HAL_GPIO_Init
|
||||
* HAL_GPIO_DeInit
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NUMBER 16U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
||||
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
||||
temp |= (GPIO_Init->Speed << (position * 2u));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Check the Pull parameter */
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3u];
|
||||
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
||||
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
||||
GPIOx->AFR[position >> 3u] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2u];
|
||||
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
||||
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
||||
SYSCFG->EXTICR[position >> 2u] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
}
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Configure the port pins */
|
||||
while ((GPIO_Pin >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2u];
|
||||
tmp &= (0x0FuL << (4u * (position & 0x03u)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
tmp = 0x0FuL << (4u * (position & 0x03u));
|
||||
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floating Mode */
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
||||
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read the specified input port pin.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or clear the selected data port bit.
|
||||
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle the specified GPIO pin.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the pin to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* get current Ouput Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bits to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
SET_BIT(tmp, GPIO_Pin);
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
/* read again in order to confirm lock is active */
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callback.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
6794
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c
Normal file
6794
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c
Normal file
365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c
Normal file
@@ -0,0 +1,365 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C Extended peripheral:
|
||||
* + Filter Mode Functions
|
||||
* + WakeUp Mode Functions
|
||||
* + FastModePlus Functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32F0xx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable wakeup from Stop mode(s)
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
|
||||
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
|
||||
(++) HAL_I2CEx_EnableWakeUp()
|
||||
(++) HAL_I2CEx_DisableWakeUp()
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_I2CEx_EnableFastModePlus()
|
||||
(++) HAL_I2CEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @brief Filter Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Filter Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Analog noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter New state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Digital noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DNF);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8U;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(I2C_CR1_WUPEN)
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
|
||||
* @brief WakeUp Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### WakeUp Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Wake Up Feature
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* I2C_CR1_WUPEN */
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @brief Fast Mode Plus Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Fast Mode Plus Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
454
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c
Normal file
454
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr.c
Normal file
@@ -0,0 +1,454 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization/de-initialization function
|
||||
* + Peripheral Control function
|
||||
*
|
||||
@verbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__HAL_RCC_PWR_FORCE_RESET();
|
||||
__HAL_RCC_PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers when present).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
PWR->CR |= (uint32_t)PWR_CR_DBP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers when present).
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
PWR->CR &= ~((uint32_t)PWR_CR_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** WakeUp pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
|
||||
forced in input pull down configuration and is active on rising edges.
|
||||
(+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices.
|
||||
(++)WakeUp Pin 1 on PA.00.
|
||||
(++)WakeUp Pin 2 on PC.13.
|
||||
(++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x)
|
||||
(++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x)
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The devices feature 3 low-power modes:
|
||||
(+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator
|
||||
in low power mode
|
||||
(+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices).
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||||
are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
|
||||
(++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
|
||||
(+) Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
(++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
|
||||
when programmed in wakeup mode (the peripheral must be
|
||||
programmed in wakeup mode and the corresponding interrupt vector
|
||||
must be enabled in the NVIC)
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M0 deep sleep mode, with the voltage regulator disabled.
|
||||
The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
|
||||
the HSE oscillator are also switched off. SRAM and register contents are lost
|
||||
except for the RTC registers, RTC backup registers and Standby circuitry.
|
||||
The voltage regulator is OFF.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||||
configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
|
||||
(++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
|
||||
(+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be value of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Enable the EWUPx pin */
|
||||
SET_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be values of :
|
||||
* @ref PWREx_WakeUp_Pins
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Disable the EWUPx pin */
|
||||
CLEAR_BIT(PWR->CSR, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param Regulator Specifies the regulator state in SLEEP mode.
|
||||
* On STM32F0 devices, this parameter is a dummy value and it is ignored
|
||||
* as regulator can't be modified in this mode. Parameter is kept for platform
|
||||
* compatibility.
|
||||
* @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator Specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
|
||||
* @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
|
||||
|
||||
/* Set LPDS bit according to Regulator value */
|
||||
tmpreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC alternate function pins if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - WKUP pins if enabled.
|
||||
* STM32F0x8 devices, the Stop mode is available, but it is
|
||||
* aningless to distinguish between voltage regulator in Low power
|
||||
* mode and voltage regulator in Run mode because the regulator
|
||||
* not used and the core is supplied directly from an external source.
|
||||
* Consequently, the Standby mode is not available on those devices.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= (uint32_t)PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M4 SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M4 SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
274
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c
Normal file
274
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c
Normal file
@@ -0,0 +1,274 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Extended Initialization and de-initialization functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWREx HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Constants PWREx Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define PVD_MODE_IT (0x00010000U)
|
||||
#define PVD_MODE_EVT (0x00020000U)
|
||||
#define PVD_RISING_EDGE (0x00000001U)
|
||||
#define PVD_FALLING_EDGE (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral extended control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
-@- PVD is not available on STM32F030x4/x6/x8
|
||||
|
||||
*** VDDIO2 Monitor Configuration ***
|
||||
====================================
|
||||
[..]
|
||||
(+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it
|
||||
to VREFInt Voltage
|
||||
(+) This monitor is internally connected to the EXTI line31
|
||||
and can generate an interrupt if enabled. This is done through
|
||||
HAL_PWREx_EnableVddio2Monitor() function.
|
||||
-@- VDDIO2 is available on STM32F07x/09x/04x
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32F031x6) || defined (STM32F051x8) || \
|
||||
defined (STM32F071xB) || defined (STM32F091xC) || \
|
||||
defined (STM32F042x6) || defined (STM32F072xB)
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
PWR->CR |= (uint32_t)PWR_CR_PVDE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
PWR->CR &= ~((uint32_t)PWR_CR_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* defined (STM32F031x6) || defined (STM32F051x8) || */
|
||||
/* defined (STM32F071xB) || defined (STM32F091xC) || */
|
||||
/* defined (STM32F042x6) || defined (STM32F072xB) */
|
||||
|
||||
#if defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx)
|
||||
/**
|
||||
* @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection.
|
||||
* @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint,
|
||||
an interrupt is generated Irq line 1.
|
||||
NVIS has to be enable by user.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableVddio2Monitor(void)
|
||||
{
|
||||
__HAL_PWR_VDDIO2_EXTI_ENABLE_IT();
|
||||
__HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Vddio2 Monitor.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableVddio2Monitor(void)
|
||||
{
|
||||
__HAL_PWR_VDDIO2_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR Vddio2 monitor interrupt request.
|
||||
* @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_Vddio2Monitor_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR Vddio2 monitor interrupt user callback */
|
||||
HAL_PWREx_Vddio2MonitorCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR Vddio2 Monitor interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWREx_Vddio2MonitorCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
|
||||
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
|
||||
defined (STM32F091xC) || defined (STM32F098xx) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c
Normal file
1365
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c
Normal file
File diff suppressed because it is too large
Load Diff
964
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c
Normal file
964
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc_ex.c
Normal file
@@ -0,0 +1,964 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
* + Extended Peripheral Control functions
|
||||
* + Extended Clock Recovery System Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
|
||||
/** @defgroup RCCEx RCCEx
|
||||
* @brief RCC Extension HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#if defined(CRS)
|
||||
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Bit position in register */
|
||||
#define CRS_CFGR_FELIM_BITNUMBER 16
|
||||
#define CRS_CR_TRIM_BITNUMBER 8
|
||||
#define CRS_ISR_FECAP_BITNUMBER 16
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRS */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the RCC Clocks
|
||||
frequencies.
|
||||
[..]
|
||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
|
||||
select the RTC clock source; in this case the Backup domain will be reset in
|
||||
order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
the backup registers) are set to their reset values.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified
|
||||
* parameters in the RCC_PeriphCLKInitTypeDef.
|
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* contains the configuration information for the Extended Peripherals clocks
|
||||
* (USART, RTC, I2C, CEC and USB).
|
||||
*
|
||||
* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
|
||||
* the RTC clock source; in this case the Backup domain will be reset in
|
||||
* order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
* the backup registers) and RCC_BDCR register are set to their reset values.
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t tickstart = 0U;
|
||||
uint32_t temp_reg = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
||||
|
||||
/*---------------------------- RTC configuration -------------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
||||
{
|
||||
/* check for RTC Parameters used to output RTCCLK */
|
||||
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
||||
|
||||
FlagStatus pwrclkchanged = RESET;
|
||||
|
||||
/* As soon as function is called to change RTC clock source, activation of the
|
||||
power domain is done. */
|
||||
/* Requires to enable write access to Backup Domain of necessary */
|
||||
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
pwrclkchanged = SET;
|
||||
}
|
||||
|
||||
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||
{
|
||||
/* Enable write access to Backup domain */
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
|
||||
/* Wait for Backup domain Write protection disable */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
||||
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
||||
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
||||
{
|
||||
/* Store the content of BDCR register before the reset of Backup Domain */
|
||||
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
/* Restore the Content of BDCR register */
|
||||
RCC->BDCR = temp_reg;
|
||||
|
||||
/* Wait for LSERDY if LSE was enabled */
|
||||
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
|
||||
{
|
||||
/* Get Start Tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till LSE is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
|
||||
/* Require to disable power clock if necessary */
|
||||
if(pwrclkchanged == SET)
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_DISABLE();
|
||||
}
|
||||
}
|
||||
|
||||
/*------------------------------- USART1 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
||||
|
||||
/* Configure the USART1 clock source */
|
||||
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
||||
}
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*----------------------------- USART2 Configuration --------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
||||
|
||||
/* Configure the USART2 clock source */
|
||||
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
||||
}
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*----------------------------- USART3 Configuration --------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
||||
|
||||
/* Configure the USART3 clock source */
|
||||
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
||||
}
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
/*------------------------------ I2C1 Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
||||
|
||||
/* Configure the I2C1 clock source */
|
||||
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
||||
}
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
|
||||
/*------------------------------ USB Configuration ------------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
||||
|
||||
/* Configure the USB clock source */
|
||||
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
||||
}
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx)\
|
||||
|| defined(STM32F051x8) || defined(STM32F058xx)\
|
||||
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
/*------------------------------ CEC clock Configuration -------------------*/
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
||||
|
||||
/* Configure the CEC clock source */
|
||||
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
||||
}
|
||||
#endif /* STM32F042x6 || STM32F048xx || */
|
||||
/* STM32F051x8 || STM32F058xx || */
|
||||
/* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the RCC_ClkInitStruct according to the internal
|
||||
* RCC configuration registers.
|
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* returns the configuration information for the Extended Peripherals clocks
|
||||
* (USART, RTC, I2C, CEC and USB).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
/* Set all possible values for the extended clock type parameter------------*/
|
||||
/* Common part first */
|
||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
|
||||
/* Get the RTC configuration --------------------------------------------*/
|
||||
PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
|
||||
/* Get the USART1 clock configuration --------------------------------------------*/
|
||||
PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
|
||||
/* Get the I2C1 clock source -----------------------------------------------*/
|
||||
PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
|
||||
|
||||
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2;
|
||||
/* Get the USART2 clock source ---------------------------------------------*/
|
||||
PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
|
||||
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F091xC) || defined(STM32F098xx)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3;
|
||||
/* Get the USART3 clock source ---------------------------------------------*/
|
||||
PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
|
||||
#endif /* STM32F091xC || STM32F098xx */
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
|
||||
/* Get the USB clock source ---------------------------------------------*/
|
||||
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
|
||||
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx)\
|
||||
|| defined(STM32F051x8) || defined(STM32F058xx)\
|
||||
|| defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
|
||||
|| defined(STM32F091xC) || defined(STM32F098xx)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
|
||||
/* Get the CEC clock source ------------------------------------------------*/
|
||||
PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
|
||||
#endif /* STM32F042x6 || STM32F048xx || */
|
||||
/* STM32F051x8 || STM32F058xx || */
|
||||
/* STM32F071xB || STM32F072xB || STM32F078xx || */
|
||||
/* STM32F091xC || STM32F098xx */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the peripheral clock frequency
|
||||
* @note Returns 0 if peripheral clock is unknown
|
||||
* @param PeriphClk Peripheral clock identifier
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
|
||||
@if STM32F042x6
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F048xx
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F051x8
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F058xx
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F070x6
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
@endif
|
||||
@if STM32F070xB
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
@endif
|
||||
@if STM32F071xB
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F072xB
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F078xx
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F091xC
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
@if STM32F098xx
|
||||
* @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_USART3 USART2 peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
|
||||
@endif
|
||||
* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
|
||||
*/
|
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
|
||||
{
|
||||
/* frequency == 0 : means that no available frequency for the peripheral */
|
||||
uint32_t frequency = 0U;
|
||||
|
||||
uint32_t srcclk = 0U;
|
||||
#if defined(USB)
|
||||
uint32_t pllmull = 0U, pllsource = 0U, predivfactor = 0U;
|
||||
#endif /* USB */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
|
||||
|
||||
switch (PeriphClk)
|
||||
{
|
||||
case RCC_PERIPHCLK_RTC:
|
||||
{
|
||||
/* Get the current RTC source */
|
||||
srcclk = __HAL_RCC_GET_RTC_SOURCE();
|
||||
|
||||
/* Check if LSE is ready and if RTC clock selection is LSE */
|
||||
if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
/* Check if LSI is ready and if RTC clock selection is LSI */
|
||||
else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
|
||||
{
|
||||
frequency = LSI_VALUE;
|
||||
}
|
||||
/* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
|
||||
else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
|
||||
{
|
||||
frequency = HSE_VALUE / 32U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case RCC_PERIPHCLK_USART1:
|
||||
{
|
||||
/* Get the current USART1 source */
|
||||
srcclk = __HAL_RCC_GET_USART1_SOURCE();
|
||||
|
||||
/* Check if USART1 clock selection is PCLK1 */
|
||||
if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
|
||||
{
|
||||
frequency = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
/* Check if HSI is ready and if USART1 clock selection is HSI */
|
||||
else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if USART1 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
/* Check if LSE is ready and if USART1 clock selection is LSE */
|
||||
else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#if defined(RCC_CFGR3_USART2SW)
|
||||
case RCC_PERIPHCLK_USART2:
|
||||
{
|
||||
/* Get the current USART2 source */
|
||||
srcclk = __HAL_RCC_GET_USART2_SOURCE();
|
||||
|
||||
/* Check if USART2 clock selection is PCLK1 */
|
||||
if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
|
||||
{
|
||||
frequency = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
/* Check if HSI is ready and if USART2 clock selection is HSI */
|
||||
else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if USART2 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
/* Check if LSE is ready and if USART2 clock selection is LSE */
|
||||
else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif /* RCC_CFGR3_USART2SW */
|
||||
#if defined(RCC_CFGR3_USART3SW)
|
||||
case RCC_PERIPHCLK_USART3:
|
||||
{
|
||||
/* Get the current USART3 source */
|
||||
srcclk = __HAL_RCC_GET_USART3_SOURCE();
|
||||
|
||||
/* Check if USART3 clock selection is PCLK1 */
|
||||
if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
|
||||
{
|
||||
frequency = HAL_RCC_GetPCLK1Freq();
|
||||
}
|
||||
/* Check if HSI is ready and if USART3 clock selection is HSI */
|
||||
else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if USART3 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
/* Check if LSE is ready and if USART3 clock selection is LSE */
|
||||
else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif /* RCC_CFGR3_USART3SW */
|
||||
case RCC_PERIPHCLK_I2C1:
|
||||
{
|
||||
/* Get the current I2C1 source */
|
||||
srcclk = __HAL_RCC_GET_I2C1_SOURCE();
|
||||
|
||||
/* Check if HSI is ready and if I2C1 clock selection is HSI */
|
||||
if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if I2C1 clock selection is SYSCLK */
|
||||
else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
|
||||
{
|
||||
frequency = HAL_RCC_GetSysClockFreq();
|
||||
}
|
||||
break;
|
||||
}
|
||||
#if defined(USB)
|
||||
case RCC_PERIPHCLK_USB:
|
||||
{
|
||||
/* Get the current USB source */
|
||||
srcclk = __HAL_RCC_GET_USB_SOURCE();
|
||||
|
||||
/* Check if PLL is ready and if USB clock selection is PLL */
|
||||
if ((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
|
||||
{
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2U;
|
||||
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
|
||||
|
||||
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
|
||||
{
|
||||
/* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */
|
||||
frequency = (HSE_VALUE/predivfactor) * pllmull;
|
||||
}
|
||||
#if defined(RCC_CR2_HSI48ON)
|
||||
else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
|
||||
{
|
||||
/* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */
|
||||
frequency = (HSI48_VALUE / predivfactor) * pllmull;
|
||||
}
|
||||
#endif /* RCC_CR2_HSI48ON */
|
||||
else
|
||||
{
|
||||
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB)
|
||||
/* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */
|
||||
frequency = (HSI_VALUE / predivfactor) * pllmull;
|
||||
#else
|
||||
/* HSI used as PLL clock source : frequency = HSI/2U * PLLMUL */
|
||||
frequency = (HSI_VALUE >> 1U) * pllmull;
|
||||
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */
|
||||
}
|
||||
}
|
||||
#if defined(RCC_CR2_HSI48ON)
|
||||
/* Check if HSI48 is ready and if USB clock selection is HSI48 */
|
||||
else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY)))
|
||||
{
|
||||
frequency = HSI48_VALUE;
|
||||
}
|
||||
#endif /* RCC_CR2_HSI48ON */
|
||||
break;
|
||||
}
|
||||
#endif /* USB */
|
||||
#if defined(CEC)
|
||||
case RCC_PERIPHCLK_CEC:
|
||||
{
|
||||
/* Get the current CEC source */
|
||||
srcclk = __HAL_RCC_GET_CEC_SOURCE();
|
||||
|
||||
/* Check if HSI is ready and if CEC clock selection is HSI */
|
||||
if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
|
||||
{
|
||||
frequency = HSI_VALUE;
|
||||
}
|
||||
/* Check if LSE is ready and if CEC clock selection is LSE */
|
||||
else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
#endif /* CEC */
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
return(frequency);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(CRS)
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
|
||||
* @brief Extended Clock Recovery System Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Clock Recovery System Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
|
||||
|
||||
(#) In System clock config, HSI48 needs to be enabled
|
||||
|
||||
(#) Enable CRS clock in IP MSP init which will use CRS functions
|
||||
|
||||
(#) Call CRS functions as follows:
|
||||
(##) Prepare synchronization configuration necessary for HSI48 calibration
|
||||
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
|
||||
and also HSI48 oscillator smooth trimming.
|
||||
(+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
|
||||
directly reload value with target and synchronization frequencies values
|
||||
(##) Call function HAL_RCCEx_CRSConfig which
|
||||
(+++) Reset CRS registers to their default values.
|
||||
(+++) Configure CRS registers with synchronization configuration
|
||||
(+++) Enable automatic calibration and frequency error counter feature
|
||||
Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
|
||||
periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
|
||||
provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
|
||||
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
|
||||
should be used as SYNC signal.
|
||||
|
||||
(##) A polling function is provided to wait for complete synchronization
|
||||
(+++) Call function HAL_RCCEx_CRSWaitSynchronization()
|
||||
(+++) According to CRS status, user can decide to adjust again the calibration or continue
|
||||
application if synchronization is OK
|
||||
|
||||
(#) User can retrieve information related to synchronization in calling function
|
||||
HAL_RCCEx_CRSGetSynchronizationInfo()
|
||||
|
||||
(#) Regarding synchronization status and synchronization information, user can try a new calibration
|
||||
in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
|
||||
Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
|
||||
it means that the actual frequency is lower than the target (and so, that the TRIM value should be
|
||||
incremented), while when it is detected during the upcounting phase it means that the actual frequency
|
||||
is higher (and that the TRIM value should be decremented).
|
||||
|
||||
(#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
|
||||
through CRS Handler (RCC_IRQn/RCC_IRQHandler)
|
||||
(++) Call function HAL_RCCEx_CRSConfig()
|
||||
(++) Enable RCC_IRQn (thanks to NVIC functions)
|
||||
(++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
|
||||
(++) Implement CRS status management in the following user callbacks called from
|
||||
HAL_RCCEx_CRS_IRQHandler():
|
||||
(+++) HAL_RCCEx_CRS_SyncOkCallback()
|
||||
(+++) HAL_RCCEx_CRS_SyncWarnCallback()
|
||||
(+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
|
||||
(+++) HAL_RCCEx_CRS_ErrorCallback()
|
||||
|
||||
(#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
|
||||
This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start automatic synchronization for polling mode
|
||||
* @param pInit Pointer on RCC_CRSInitTypeDef structure
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
|
||||
{
|
||||
uint32_t value = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
|
||||
assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
|
||||
assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
|
||||
assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
|
||||
assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
|
||||
assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
|
||||
|
||||
/* CONFIGURATION */
|
||||
|
||||
/* Before configuration, reset CRS registers to their default values*/
|
||||
__HAL_RCC_CRS_FORCE_RESET();
|
||||
__HAL_RCC_CRS_RELEASE_RESET();
|
||||
|
||||
/* Set the SYNCDIV[2:0] bits according to Prescaler value */
|
||||
/* Set the SYNCSRC[1:0] bits according to Source value */
|
||||
/* Set the SYNCSPOL bit according to Polarity value */
|
||||
value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
|
||||
/* Set the RELOAD[15:0] bits according to ReloadValue value */
|
||||
value |= pInit->ReloadValue;
|
||||
/* Set the FELIM[7:0] bits according to ErrorLimitValue value */
|
||||
value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
|
||||
WRITE_REG(CRS->CFGR, value);
|
||||
|
||||
/* Adjust HSI48 oscillator smooth trimming */
|
||||
/* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER));
|
||||
|
||||
/* START AUTOMATIC SYNCHRONIZATION*/
|
||||
|
||||
/* Enable Automatic trimming & Frequency error counter */
|
||||
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate the software synchronization event
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return synchronization info
|
||||
* @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(pSynchroInfo != NULL);
|
||||
|
||||
/* Get the reload value */
|
||||
pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
|
||||
|
||||
/* Get HSI48 oscillator smooth trimming */
|
||||
pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
|
||||
|
||||
/* Get Frequency error capture */
|
||||
pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
|
||||
|
||||
/* Get Frequency error direction */
|
||||
pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for CRS Synchronization status.
|
||||
* @param Timeout Duration of the timeout
|
||||
* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
|
||||
* frequency.
|
||||
* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
|
||||
* @retval Combination of Synchronization status
|
||||
* This parameter can be a combination of the following values:
|
||||
* @arg @ref RCC_CRS_TIMEOUT
|
||||
* @arg @ref RCC_CRS_SYNCOK
|
||||
* @arg @ref RCC_CRS_SYNCWARN
|
||||
* @arg @ref RCC_CRS_SYNCERR
|
||||
* @arg @ref RCC_CRS_SYNCMISS
|
||||
* @arg @ref RCC_CRS_TRIMOVF
|
||||
*/
|
||||
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
|
||||
{
|
||||
uint32_t crsstatus = RCC_CRS_NONE;
|
||||
uint32_t tickstart = 0U;
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for CRS flag or timeout detection */
|
||||
do
|
||||
{
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
|
||||
{
|
||||
crsstatus = RCC_CRS_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Check CRS SYNCOK flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
|
||||
{
|
||||
/* CRS SYNC event OK */
|
||||
crsstatus |= RCC_CRS_SYNCOK;
|
||||
|
||||
/* Clear CRS SYNC event OK bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
|
||||
}
|
||||
|
||||
/* Check CRS SYNCWARN flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
|
||||
{
|
||||
/* CRS SYNC warning */
|
||||
crsstatus |= RCC_CRS_SYNCWARN;
|
||||
|
||||
/* Clear CRS SYNCWARN bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
|
||||
}
|
||||
|
||||
/* Check CRS TRIM overflow flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
|
||||
{
|
||||
/* CRS SYNC Error */
|
||||
crsstatus |= RCC_CRS_TRIMOVF;
|
||||
|
||||
/* Clear CRS Error bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
|
||||
}
|
||||
|
||||
/* Check CRS Error flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
|
||||
{
|
||||
/* CRS SYNC Error */
|
||||
crsstatus |= RCC_CRS_SYNCERR;
|
||||
|
||||
/* Clear CRS Error bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
|
||||
}
|
||||
|
||||
/* Check CRS SYNC Missed flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
|
||||
{
|
||||
/* CRS SYNC Missed */
|
||||
crsstatus |= RCC_CRS_SYNCMISS;
|
||||
|
||||
/* Clear CRS SYNC Missed bit */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
|
||||
}
|
||||
|
||||
/* Check CRS Expected SYNC flag */
|
||||
if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
|
||||
{
|
||||
/* frequency error counter reached a zero value */
|
||||
__HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
|
||||
}
|
||||
} while(RCC_CRS_NONE == crsstatus);
|
||||
|
||||
return crsstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle the Clock Recovery System interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_CRS_IRQHandler(void)
|
||||
{
|
||||
uint32_t crserror = RCC_CRS_NONE;
|
||||
/* Get current IT flags and IT sources values */
|
||||
uint32_t itflags = READ_REG(CRS->ISR);
|
||||
uint32_t itsources = READ_REG(CRS->CR);
|
||||
|
||||
/* Check CRS SYNCOK flag */
|
||||
if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET))
|
||||
{
|
||||
/* Clear CRS SYNC event OK flag */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
|
||||
|
||||
/* user callback */
|
||||
HAL_RCCEx_CRS_SyncOkCallback();
|
||||
}
|
||||
/* Check CRS SYNCWARN flag */
|
||||
else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET))
|
||||
{
|
||||
/* Clear CRS SYNCWARN flag */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
|
||||
|
||||
/* user callback */
|
||||
HAL_RCCEx_CRS_SyncWarnCallback();
|
||||
}
|
||||
/* Check CRS Expected SYNC flag */
|
||||
else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET))
|
||||
{
|
||||
/* frequency error counter reached a zero value */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
|
||||
|
||||
/* user callback */
|
||||
HAL_RCCEx_CRS_ExpectedSyncCallback();
|
||||
}
|
||||
/* Check CRS Error flags */
|
||||
else
|
||||
{
|
||||
if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET))
|
||||
{
|
||||
if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET)
|
||||
{
|
||||
crserror |= RCC_CRS_SYNCERR;
|
||||
}
|
||||
if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET)
|
||||
{
|
||||
crserror |= RCC_CRS_SYNCMISS;
|
||||
}
|
||||
if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET)
|
||||
{
|
||||
crserror |= RCC_CRS_TRIMOVF;
|
||||
}
|
||||
|
||||
/* Clear CRS Error flags */
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
|
||||
|
||||
/* user error callback */
|
||||
HAL_RCCEx_CRS_ErrorCallback(crserror);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx Clock Recovery System Error interrupt callback.
|
||||
* @param Error Combination of Error status.
|
||||
* This parameter can be a combination of the following values:
|
||||
* @arg @ref RCC_CRS_SYNCERR
|
||||
* @arg @ref RCC_CRS_SYNCMISS
|
||||
* @arg @ref RCC_CRS_TRIMOVF
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Error);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CRS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
7635
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c
Normal file
7635
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c
Normal file
File diff suppressed because it is too large
Load Diff
2390
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c
Normal file
2390
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim_ex.c
Normal file
File diff suppressed because it is too large
Load Diff
4128
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c
Normal file
4128
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart.c
Normal file
File diff suppressed because it is too large
Load Diff
816
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c
Normal file
816
Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_uart_ex.c
Normal file
@@ -0,0 +1,816 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_hal_uart_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended UART HAL module driver.
|
||||
* This file provides firmware functions to manage the following extended
|
||||
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### UART peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
(#) Declare a UART_HandleTypeDef handle structure.
|
||||
|
||||
(#) For the UART RS485 Driver Enable mode, initialize the UART registers
|
||||
by calling the HAL_RS485Ex_Init() API.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx UARTEx
|
||||
* @brief UART Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_UESM)
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Extended Initialization and Configuration Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
|
||||
in asynchronous mode.
|
||||
(+) For the asynchronous mode the parameters below can be configured:
|
||||
(++) Baud Rate
|
||||
(++) Word Length
|
||||
(++) Stop Bit
|
||||
(++) Parity: If the parity is enabled, then the MSB bit of the data written
|
||||
in the data register is transmitted but is changed by the parity bit.
|
||||
(++) Hardware flow control
|
||||
(++) Receiver/transmitter modes
|
||||
(++) Over Sampling Method
|
||||
(++) One-Bit Sampling Method
|
||||
(+) For the asynchronous mode, the following advanced features can be configured as well:
|
||||
(++) TX and/or RX pin level inversion
|
||||
(++) data logical level inversion
|
||||
(++) RX and TX pins swap
|
||||
(++) RX overrun detection disabling
|
||||
(++) DMA disabling on RX error
|
||||
(++) MSB first on communication line
|
||||
(++) auto Baud rate detection
|
||||
[..]
|
||||
The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
|
||||
procedures (details for the procedures are available in reference manual).
|
||||
|
||||
@endverbatim
|
||||
|
||||
Depending on the frame length defined by the M1 and M0 bits (7-bit,
|
||||
8-bit or 9-bit), the possible UART formats are listed in the
|
||||
following table.
|
||||
|
||||
Table 1. UART frame format.
|
||||
+-----------------------------------------------------------------------+
|
||||
| M1 bit | M0 bit | PCE bit | UART frame |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
|
||||
+-----------------------------------------------------------------------+
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the RS485 Driver enable feature according to the specified
|
||||
* parameters in the UART_InitTypeDef and creates the associated handle.
|
||||
* @param huart UART handle.
|
||||
* @param Polarity Select the driver enable polarity.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
|
||||
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
|
||||
* @param AssertionTime Driver Enable assertion time:
|
||||
* 5-bit value defining the time between the activation of the DE (Driver Enable)
|
||||
* signal and the beginning of the start bit. It is expressed in sample time
|
||||
* units (1/8 or 1/16 bit time, depending on the oversampling rate)
|
||||
* @param DeassertionTime Driver Enable deassertion time:
|
||||
* 5-bit value defining the time between the end of the last stop bit, in a
|
||||
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
|
||||
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
|
||||
* oversampling rate).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
|
||||
uint32_t DeassertionTime)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the Driver Enable UART instance */
|
||||
assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
|
||||
|
||||
/* Check the Driver Enable polarity */
|
||||
assert_param(IS_UART_DE_POLARITY(Polarity));
|
||||
|
||||
/* Check the Driver Enable assertion time */
|
||||
assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
|
||||
|
||||
/* Check the Driver Enable deassertion time */
|
||||
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
huart->Lock = HAL_UNLOCKED;
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
UART_InitCallbacksToDefault(huart);
|
||||
|
||||
if (huart->MspInitCallback == NULL)
|
||||
{
|
||||
huart->MspInitCallback = HAL_UART_MspInit;
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
huart->MspInitCallback(huart);
|
||||
#else
|
||||
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
|
||||
HAL_UART_MspInit(huart);
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
||||
|
||||
/* Set the Driver Enable polarity */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
|
||||
|
||||
/* Set the Driver Enable assertion and deassertion times */
|
||||
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
|
||||
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
|
||||
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
|
||||
* @brief Extended functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
This subsection provides a set of Wakeup and FIFO mode related callback functions.
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
(#) Wakeup from Stop mode Callback:
|
||||
(+) HAL_UARTEx_WakeupCallback()
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
#if defined(USART_CR3_WUFIE)
|
||||
/**
|
||||
* @brief UART wakeup from Stop mode callback.
|
||||
* @param huart UART handle.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(huart);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_WUFIE */
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides the following functions:
|
||||
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
|
||||
detection length to more than 4 bits for multiprocessor address mark wake up.
|
||||
#if defined(USART_CR1_UESM)
|
||||
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
|
||||
trigger: address match, Start Bit detection or RXNE bit status.
|
||||
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
|
||||
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
|
||||
#endif
|
||||
|
||||
[..] This subsection also provides a set of additional functions providing enhanced reception
|
||||
services to user. (For example, these functions allow application to handle use cases
|
||||
where number of data to be received is unknown).
|
||||
|
||||
(#) Compared to standard reception services which only consider number of received
|
||||
data elements as reception completion criteria, these functions also consider additional events
|
||||
as triggers for updating reception status to caller :
|
||||
(+) Detection of inactivity period (RX line has not been active for a given period).
|
||||
(++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
|
||||
for 1 frame time, after last received byte.
|
||||
(++) RX inactivity detected by RTO, i.e. line has been in idle state
|
||||
for a programmable time, after last received byte.
|
||||
(+) Detection that a specific character has been received.
|
||||
|
||||
(#) There are two mode of transfer:
|
||||
(+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
|
||||
or till IDLE event occurs. Reception is handled only during function execution.
|
||||
When function exits, no data reception could occur. HAL status and number of actually received data elements,
|
||||
are returned by function after finishing transfer.
|
||||
(+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
|
||||
These API's return the HAL status.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
|
||||
The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
|
||||
The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
|
||||
|
||||
(#) Blocking mode API:
|
||||
(+) HAL_UARTEx_ReceiveToIdle()
|
||||
|
||||
(#) Non-Blocking mode API with Interrupt:
|
||||
(+) HAL_UARTEx_ReceiveToIdle_IT()
|
||||
|
||||
(#) Non-Blocking mode API with DMA:
|
||||
(+) HAL_UARTEx_ReceiveToIdle_DMA()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief By default in multiprocessor mode, when the wake up method is set
|
||||
* to address mark, the UART handles only 4-bit long addresses detection;
|
||||
* this API allows to enable longer addresses detection (6-, 7- or 8-bit
|
||||
* long).
|
||||
* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
|
||||
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
|
||||
* @param huart UART handle.
|
||||
* @param AddressLength This parameter can be one of the following values:
|
||||
* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
|
||||
* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
|
||||
{
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the address length parameter */
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
/**
|
||||
* @brief Set Wakeup from Stop mode interrupt flag selection.
|
||||
* @note It is the application responsibility to enable the interrupt used as
|
||||
* usart_wkup interrupt source before entering low-power mode.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_WAKEUP_ON_ADDRESS
|
||||
* @arg @ref UART_WAKEUP_ON_STARTBIT
|
||||
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* check the wake-up from stop mode UART instance */
|
||||
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
|
||||
/* check the wake-up selection parameter */
|
||||
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
#if defined(USART_CR3_WUS)
|
||||
/* Set the wake-up selection scheme */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
|
||||
#endif /* USART_CR3_WUS */
|
||||
|
||||
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
|
||||
{
|
||||
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until REACK flag is set */
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||||
{
|
||||
status = HAL_TIMEOUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the UART State */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable UART Stop Mode.
|
||||
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set UESM bit */
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable UART Stop Mode.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Clear UESM bit */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @brief Receive an amount of data in blocking mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note HAL_OK is returned if reception is completed (expected number of data has been received)
|
||||
* or if reception is stopped after IDLE event (less than the expected number of data has been received)
|
||||
* In this case, RxLen output parameter indicates number of data available in reception buffer.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required to ensure proper
|
||||
* alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @param RxLen Number of data elements finally received
|
||||
* (could be lower than Size, in case reception ends on IDLE event)
|
||||
* @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint8_t *pdata8bits;
|
||||
uint16_t *pdata16bits;
|
||||
uint16_t uhMask;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
|
||||
should be aligned on a uint16_t frontier, as data to be received from RDR will be
|
||||
handled through a uint16_t cast. */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
if ((((uint32_t)pData) & 1U) != 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
||||
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
huart->RxXferSize = Size;
|
||||
huart->RxXferCount = Size;
|
||||
|
||||
/* Computation of UART mask to apply to RDR register */
|
||||
UART_MASK_COMPUTATION(huart);
|
||||
uhMask = huart->Mask;
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
pdata8bits = NULL;
|
||||
pdata16bits = (uint16_t *) pData;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdata8bits = pData;
|
||||
pdata16bits = NULL;
|
||||
}
|
||||
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Initialize output number of received elements */
|
||||
*RxLen = 0U;
|
||||
|
||||
/* as long as data have to be received */
|
||||
while (huart->RxXferCount > 0U)
|
||||
{
|
||||
/* Check if IDLE flag is set */
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
|
||||
{
|
||||
/* Clear IDLE flag in ISR */
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
|
||||
/* If Set, but no data ever received, clear flag without exiting loop */
|
||||
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
|
||||
if (*RxLen > 0U)
|
||||
{
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if RXNE flag is set */
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
|
||||
{
|
||||
if (pdata8bits == NULL)
|
||||
{
|
||||
*pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
|
||||
pdata16bits++;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
|
||||
pdata8bits++;
|
||||
}
|
||||
/* Increment number of received elements */
|
||||
*RxLen += 1U;
|
||||
huart->RxXferCount--;
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Set number of received elements in output parameter : RxLen */
|
||||
*RxLen = huart->RxXferSize - huart->RxXferCount;
|
||||
/* At end of Rx process, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in interrupt mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
|
||||
* number of received data elements.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
|
||||
should be aligned on a uint16_t frontier, as data to be received from RDR will be
|
||||
handled through a uint16_t cast. */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
if ((((uint32_t)pData) & 1U) != 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set Reception type to reception till IDLE Event*/
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
|
||||
status = UART_Start_Receive_IT(huart, pData, Size);
|
||||
|
||||
/* Check Rx process has been successfully started */
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in DMA mode till either the expected number
|
||||
* of data is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to DMA services, transferring automatically received data elements in user reception buffer and
|
||||
* calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
|
||||
* reception phase as ended. In all cases, callback execution will indicate number of received data elements.
|
||||
* @note When the UART parity is enabled (PCE = 1), the received data contain
|
||||
* the parity bit (MSB position).
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* address of user data buffer for storing data to be received, should be aligned on a half word frontier
|
||||
* (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
|
||||
* use of specific alignment compilation directives or pragmas might be required
|
||||
* to ensure proper alignment for pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
|
||||
should be aligned on a uint16_t frontier, as data copy from RDR will be
|
||||
handled by DMA from a uint16_t frontier. */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
if ((((uint32_t)pData) & 1U) != 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set Reception type to reception till IDLE Event*/
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
|
||||
status = UART_Start_Receive_DMA(huart, pData, Size);
|
||||
|
||||
/* Check Rx process has been successfully started */
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_UESM)
|
||||
|
||||
/**
|
||||
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection UART wake up from stop mode parameters.
|
||||
* @retval None
|
||||
*/
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
|
||||
|
||||
/* Set the USART address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
|
||||
|
||||
/* Set the USART address node */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
|
||||
}
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user